st,flexgen.txt

  1Binding for a type of flexgen structure found on certain
  2STMicroelectronics consumer electronics SoC devices
  3
  4This structure includes:
  5- a clock cross bar (represented by a mux element)
  6- a pre and final dividers (represented by a divider and gate elements)
  7
  8Flexgen structure is a part of Clockgen[1].
  9
 10Please find an example below:
 11
 12    Clockgen block diagram
 13    -------------------------------------------------------------------
 14   |                     Flexgen structure                             |
 15   |                  ---------------------------------------------    |
 16   |                 |    -------       --------       --------    |   |
 17clk_sysin            |   |       |     |        |     |        |   |   |
 18---|-----------------|-->|       |     |        |     |        |   |   |
 19   | |               |   |       |     |        |     |        |   |   |
 20   | |   -------     |   |       |     |Pre     |     |Final   |   |   |
 21   | |  |PLL0   |    |   |       |     |Dividers|     |Dividers|   |   |
 22   | |->|       |    |   |       |     |  x32   |     |  x32   |   |   |
 23   | |  |  odf_0|----|-->|       |     |        |     |        |   |   |
 24   | |  |       |    |   |       |     |        |     |        |   |   |
 25   | |  |       |    |   |       |     |        |     |        |   |   |
 26   | |  |       |    |   |       |     |        |     |        |   |   |
 27   | |  |       |    |   |       |     |        |     |        |   |   |
 28   | |   -------     |   |       |     |        |     |        |   |   |
 29   | |               |   |       |     |        |     |        |   |   |
 30   | |   -------     |   | Clock |     |        |     |        |   |   |
 31   | |  |PLL1   |    |   |       |     |        |     |        |   |   |
 32   | |->|       |    |   | Cross |     |        |     |        |   |   |
 33   | |  |  odf_0|----|-->|       |     |        |     |        | CLK_DIV[31:0]
 34   | |  |       |    |   | Bar   |====>|        |====>|        |===|=========>
 35   | |  |       |    |   |       |     |        |     |        |   |   |
 36   | |  |       |    |   |       |     |        |     |        |   |   |
 37   | |  |       |    |   |       |     |        |     |        |   |   |
 38   | |   -------     |   |       |     |        |     |        |   |   |
 39   | |               |   |       |     |        |     |        |   |   |
 40   | |   -------     |   |       |     |        |     |        |   |   |
 41   | |  |QUADFS |    |   |       |     |        |     |        |   |   |
 42   | |->|    ch0|----|-->|       |     |        |     |        |   |   |
 43   |    |       |    |   |       |     |        |     |        |   |   |
 44   |    |    ch1|----|-->|       |     |        |     |        |   |   |
 45   |    |       |    |   |       |     |        |     |        |   |   |
 46   |    |    ch2|----|-->|       |     | DIV    |     | DIV    |   |   |
 47   |    |       |    |   |       |     |  1 to  |     |  1 to  |   |   |
 48   |    |    ch3|----|-->|       |     |   1024 |     |     64 |   |   |
 49   |     -------     |   |       |     |        |     |        |   |   |
 50   |                 |    -------       --------       --------    |   |
 51   |                   --------------------------------------------    |
 52   |                                                                   |
 53    -------------------------------------------------------------------
 54
 55This binding uses the common clock binding[2].
 56
 57[1] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
 58[2] Documentation/devicetree/bindings/clock/clock-bindings.txt
 59
 60Required properties:
 61- compatible : shall be:
 62  "st,flexgen"
 63  "st,flexgen-audio", "st,flexgen" (enable clock propagation on parent for
 64  audio use case)
 65  "st,flexgen-video", "st,flexgen" (enable clock propagation on parent
 66					and activate synchronous mode)
 67  "st,flexgen-stih410-a0"
 68  "st,flexgen-stih410-c0"
 69  "st,flexgen-stih418-c0"
 70  "st,flexgen-stih410-d0"
 71  "st,flexgen-stih407-d2"
 72  "st,flexgen-stih418-d2"
 73  "st,flexgen-stih407-d3"
 74
 75- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
 76  outputs).
 77
 78- clocks : must be set to the parent's phandle. it could be output clocks of
 79  a quadsfs or/and a pll or/and clk_sysin (up to 7 clocks)
 80
 81- clock-output-names : List of strings used to name the clock outputs.
 82
 83Example:
 84
 85	clk_s_c0_flexgen: clk-s-c0-flexgen {
 86
 87		#clock-cells = <1>;
 88		compatible = "st,flexgen";
 89
 90		clocks = <&clk_s_c0_pll0 0>,
 91			 <&clk_s_c0_pll1 0>,
 92			 <&clk_s_c0_quadfs 0>,
 93			 <&clk_s_c0_quadfs 1>,
 94			 <&clk_s_c0_quadfs 2>,
 95			 <&clk_s_c0_quadfs 3>,
 96			 <&clk_sysin>;
 97
 98		clock-output-names = "clk-icn-gpu",
 99				     "clk-fdma",
100				     "clk-nand",
101				     "clk-hva",
102				     "clk-proc-stfe",
103				     "clk-proc-tp",
104				     "clk-rx-icn-dmu",
105				     "clk-rx-icn-hva",
106				     "clk-icn-cpu",
107				     "clk-tx-icn-dmu",
108				     "clk-mmc-0",
109				     "clk-mmc-1",
110				     "clk-jpegdec",
111				     "clk-ext2fa9",
112				     "clk-ic-bdisp-0",
113				     "clk-ic-bdisp-1",
114				     "clk-pp-dmu",
115				     "clk-vid-dmu",
116				     "clk-dss-lpc",
117				     "clk-st231-aud-0",
118				     "clk-st231-gp-1",
119				     "clk-st231-dmu",
120				     "clk-icn-lmi",
121				     "clk-tx-icn-disp-1",
122				     "clk-icn-sbc",
123				     "clk-stfe-frc2",
124				     "clk-eth-phy",
125				     "clk-eth-ref-phyclk",
126				     "clk-flash-promip",
127				     "clk-main-disp",
128				     "clk-aux-disp",
129				     "clk-compo-dvp";
130	};