renesas,cpg-clocks.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Renesas Clock Pulse Generator (CPG)
  8
  9maintainers:
 10  - Geert Uytterhoeven <geert+renesas@glider.be>
 11
 12description:
 13  The Clock Pulse Generator (CPG) generates core clocks for the SoC.  It
 14  includes PLLs, and fixed and variable ratio dividers.
 15
 16  The CPG may also provide a Clock Domain for SoC devices, in combination with
 17  the CPG Module Stop (MSTP) Clocks.
 18
 19properties:
 20  compatible:
 21    oneOf:
 22      - const: renesas,r8a73a4-cpg-clocks     # R-Mobile APE6
 23      - const: renesas,r8a7740-cpg-clocks     # R-Mobile A1
 24      - const: renesas,r8a7778-cpg-clocks     # R-Car M1
 25      - const: renesas,r8a7779-cpg-clocks     # R-Car H1
 26      - items:
 27          - enum:
 28              - renesas,r7s72100-cpg-clocks   # RZ/A1H
 29          - const: renesas,rz-cpg-clocks      # RZ/A1
 30      - const: renesas,sh73a0-cpg-clocks      # SH-Mobile AG5
 31
 32  reg:
 33    maxItems: 1
 34
 35  clocks:
 36    minItems: 1
 37    maxItems: 3
 38
 39  '#clock-cells':
 40    const: 1
 41
 42  clock-output-names:
 43    minItems: 3
 44    maxItems: 17
 45
 46  renesas,mode:
 47    description: Board-specific settings of the MD_CK* bits on R-Mobile A1
 48    $ref: /schemas/types.yaml#/definitions/uint32
 49    minimum: 0
 50    maximum: 7
 51
 52  '#power-domain-cells':
 53    const: 0
 54
 55required:
 56  - compatible
 57  - reg
 58  - clocks
 59  - '#clock-cells'
 60  - clock-output-names
 61
 62allOf:
 63  - if:
 64      properties:
 65        compatible:
 66          contains:
 67            const: renesas,r8a73a4-cpg-clocks
 68    then:
 69      properties:
 70        clocks:
 71          items:
 72            - description: extal1
 73            - description: extal2
 74
 75        clock-output-names:
 76          items:
 77            - const: main
 78            - const: pll0
 79            - const: pll1
 80            - const: pll2
 81            - const: pll2s
 82            - const: pll2h
 83            - const: z
 84            - const: z2
 85            - const: i
 86            - const: m3
 87            - const: b
 88            - const: m1
 89            - const: m2
 90            - const: zx
 91            - const: zs
 92            - const: hp
 93
 94  - if:
 95      properties:
 96        compatible:
 97          contains:
 98            const: renesas,r8a7740-cpg-clocks
 99    then:
100      properties:
101        clocks:
102          items:
103            - description: extal1
104            - description: extal2
105            - description: extalr
106
107        clock-output-names:
108          items:
109            - const: system
110            - const: pllc0
111            - const: pllc1
112            - const: pllc2
113            - const: r
114            - const: usb24s
115            - const: i
116            - const: zg
117            - const: b
118            - const: m1
119            - const: hp
120            - const: hpp
121            - const: usbp
122            - const: s
123            - const: zb
124            - const: m3
125            - const: cp
126
127      required:
128        - renesas,mode
129
130  - if:
131      properties:
132        compatible:
133          contains:
134            const: renesas,r8a7778-cpg-clocks
135    then:
136      properties:
137        clocks:
138          maxItems: 1
139
140        clock-output-names:
141          items:
142            - const: plla
143            - const: pllb
144            - const: b
145            - const: out
146            - const: p
147            - const: s
148            - const: s1
149
150  - if:
151      properties:
152        compatible:
153          contains:
154            const: renesas,r8a7779-cpg-clocks
155    then:
156      properties:
157        clocks:
158          maxItems: 1
159
160        clock-output-names:
161          items:
162            - const: plla
163            - const: z
164            - const: zs
165            - const: s
166            - const: s1
167            - const: p
168            - const: b
169            - const: out
170
171  - if:
172      properties:
173        compatible:
174          contains:
175            const: renesas,r7s72100-cpg-clocks
176    then:
177      properties:
178        clocks:
179          items:
180            - description: extal1
181            - description: usb_x1
182
183        clock-output-names:
184          items:
185            - const: pll
186            - const: i
187            - const: g
188
189  - if:
190      properties:
191        compatible:
192          contains:
193            const: renesas,sh73a0-cpg-clocks
194    then:
195      properties:
196        clocks:
197          items:
198            - description: extal1
199            - description: extal2
200
201        clock-output-names:
202          items:
203            - const: main
204            - const: pll0
205            - const: pll1
206            - const: pll2
207            - const: pll3
208            - const: dsi0phy
209            - const: dsi1phy
210            - const: zg
211            - const: m3
212            - const: b
213            - const: m1
214            - const: m2
215            - const: z
216            - const: zx
217            - const: hp
218
219  - if:
220      properties:
221        compatible:
222          contains:
223            enum:
224              - renesas,r8a7778-cpg-clocks
225              - renesas,r8a7779-cpg-clocks
226              - renesas,rz-cpg-clocks
227    then:
228      required:
229        - '#power-domain-cells'
230
231additionalProperties: false
232
233examples:
234  - |
235    #include <dt-bindings/clock/r8a7740-clock.h>
236    cpg_clocks: cpg_clocks@e6150000 {
237            compatible = "renesas,r8a7740-cpg-clocks";
238            reg = <0xe6150000 0x10000>;
239            clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
240            #clock-cells = <1>;
241            clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
242                                 "usb24s", "i", "zg", "b", "m1", "hp", "hpp",
243                                 "usbp", "s", "zb", "m3", "cp";
244            renesas,mode = <0x05>;
245    };