qcom,x1e80100-gcc.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/clock/qcom,x1e80100-gcc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Global Clock & Reset Controller on X1E80100
  8
  9maintainers:
 10  - Rajendra Nayak <quic_rjendra@quicinc.com>
 11
 12description: |
 13  Qualcomm global clock control module provides the clocks, resets and power
 14  domains on X1E80100
 15
 16  See also: include/dt-bindings/clock/qcom,x1e80100-gcc.h
 17
 18properties:
 19  compatible:
 20    oneOf:
 21      - items:
 22          - const: qcom,x1p42100-gcc
 23          - const: qcom,x1e80100-gcc
 24      - const: qcom,x1e80100-gcc
 25
 26  clocks:
 27    items:
 28      - description: Board XO source
 29      - description: Sleep clock source
 30      - description: PCIe 3 pipe clock
 31      - description: PCIe 4 pipe clock
 32      - description: PCIe 5 pipe clock
 33      - description: PCIe 6a pipe clock
 34      - description: PCIe 6b pipe clock
 35      - description: USB4_0 QMPPHY clock source
 36      - description: USB4_1 QMPPHY clock source
 37      - description: USB4_2 QMPPHY clock source
 38      - description: USB4_0 PHY DP0 GMUX clock source
 39      - description: USB4_0 PHY DP1 GMUX clock source
 40      - description: USB4_0 PHY PCIE PIPEGMUX clock source
 41      - description: USB4_0 PHY PIPEGMUX clock source
 42      - description: USB4_0 PHY SYS PCIE PIPEGMUX clock source
 43      - description: USB4_1 PHY DP0 GMUX 2 clock source
 44      - description: USB4_1 PHY DP1 GMUX 2 clock source
 45      - description: USB4_1 PHY PCIE PIPEGMUX clock source
 46      - description: USB4_1 PHY PIPEGMUX clock source
 47      - description: USB4_1 PHY SYS PCIE PIPEGMUX clock source
 48      - description: USB4_2 PHY DP0 GMUX 2 clock source
 49      - description: USB4_2 PHY DP1 GMUX 2 clock source
 50      - description: USB4_2 PHY PCIE PIPEGMUX clock source
 51      - description: USB4_2 PHY PIPEGMUX clock source
 52      - description: USB4_2 PHY SYS PCIE PIPEGMUX clock source
 53      - description: USB4_0 PHY RX 0 clock source
 54      - description: USB4_0 PHY RX 1 clock source
 55      - description: USB4_1 PHY RX 0 clock source
 56      - description: USB4_1 PHY RX 1 clock source
 57      - description: USB4_2 PHY RX 0 clock source
 58      - description: USB4_2 PHY RX 1 clock source
 59      - description: USB4_0 PHY PCIE PIPE clock source
 60      - description: USB4_0 PHY max PIPE clock source
 61      - description: USB4_1 PHY PCIE PIPE clock source
 62      - description: USB4_1 PHY max PIPE clock source
 63      - description: USB4_2 PHY PCIE PIPE clock source
 64      - description: USB4_2 PHY max PIPE clock source
 65
 66  power-domains:
 67    description:
 68      A phandle and PM domain specifier for the CX power domain.
 69    maxItems: 1
 70
 71required:
 72  - compatible
 73  - clocks
 74  - power-domains
 75  - '#power-domain-cells'
 76
 77allOf:
 78  - $ref: qcom,gcc.yaml#
 79
 80unevaluatedProperties: false
 81
 82examples:
 83  - |
 84    #include <dt-bindings/power/qcom,rpmhpd.h>
 85    clock-controller@100000 {
 86      compatible = "qcom,x1e80100-gcc";
 87      reg = <0x00100000 0x200000>;
 88      clocks = <&bi_tcxo_div2>,
 89               <&sleep_clk>,
 90               <&pcie3_phy>,
 91               <&pcie4_phy>,
 92               <&pcie5_phy>,
 93               <&pcie6a_phy>,
 94               <&pcie6b_phy>,
 95               <&usb_1_ss0_qmpphy 0>,
 96               <&usb_1_ss1_qmpphy 1>,
 97               <&usb_1_ss2_qmpphy 2>,
 98               <&usb4_0_phy_dp0_gmux_clk>,
 99               <&usb4_0_phy_dp1_gmux_clk>,
100               <&usb4_0_phy_pcie_pipegmux_clk>,
101               <&usb4_0_phy_pipegmux_clk>,
102               <&usb4_0_phy_sys_pcie_pipegmux_clk>,
103               <&usb4_1_phy_dp0_gmux_2_clk>,
104               <&usb4_1_phy_dp1_gmux_2_clk>,
105               <&usb4_1_phy_pcie_pipegmux_clk>,
106               <&usb4_1_phy_pipegmux_clk>,
107               <&usb4_1_phy_sys_pcie_pipegmux_clk>,
108               <&usb4_2_phy_dp0_gmux_2_clk>,
109               <&usb4_2_phy_dp1_gmux_2_clk>,
110               <&usb4_2_phy_pcie_pipegmux_clk>,
111               <&usb4_2_phy_pipegmux_clk>,
112               <&usb4_2_phy_sys_pcie_pipegmux_clk>,
113               <&usb4_0_phy_rx_0_clk>,
114               <&usb4_0_phy_rx_1_clk>,
115               <&usb4_1_phy_rx_0_clk>,
116               <&usb4_1_phy_rx_1_clk>,
117               <&usb4_2_phy_rx_0_clk>,
118               <&usb4_2_phy_rx_1_clk>,
119               <&usb4_0_phy_pcie_pipe_clk>,
120               <&usb4_0_phy_max_pipe_clk>,
121               <&usb4_1_phy_pcie_pipe_clk>,
122               <&usb4_1_phy_max_pipe_clk>,
123               <&usb4_2_phy_pcie_pipe_clk>,
124               <&usb4_2_phy_max_pipe_clk>;
125      power-domains = <&rpmhpd RPMHPD_CX>;
126      #clock-cells = <1>;
127      #reset-cells = <1>;
128      #power-domain-cells = <1>;
129    };
130
131...