qcom,sm8550-dispcc.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Display Clock & Reset Controller for SM8550
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11  - Neil Armstrong <neil.armstrong@linaro.org>
 12
 13description: |
 14  Qualcomm display clock control module provides the clocks, resets and power
 15  domains on SM8550, SM8650, SM8750 and few other platforms.
 16
 17  See also:
 18  - include/dt-bindings/clock/qcom,sm8550-dispcc.h
 19  - include/dt-bindings/clock/qcom,sm8650-dispcc.h
 20  - include/dt-bindings/clock/qcom,sm8750-dispcc.h
 21  - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
 22
 23properties:
 24  compatible:
 25    enum:
 26      - qcom,sar2130p-dispcc
 27      - qcom,sm8550-dispcc
 28      - qcom,sm8650-dispcc
 29      - qcom,sm8750-dispcc
 30      - qcom,x1e80100-dispcc
 31
 32  clocks:
 33    items:
 34      - description: Board XO source
 35      - description: Board Always On XO source
 36      - description: Display's AHB clock
 37      - description: sleep clock
 38      - description: Byte clock from DSI PHY0
 39      - description: Pixel clock from DSI PHY0
 40      - description: Byte clock from DSI PHY1
 41      - description: Pixel clock from DSI PHY1
 42      - description: Link clock from DP PHY0
 43      - description: VCO DIV clock from DP PHY0
 44      - description: Link clock from DP PHY1
 45      - description: VCO DIV clock from DP PHY1
 46      - description: Link clock from DP PHY2
 47      - description: VCO DIV clock from DP PHY2
 48      - description: Link clock from DP PHY3
 49      - description: VCO DIV clock from DP PHY3
 50
 51  power-domains:
 52    description:
 53      A phandle and PM domain specifier for the MMCX power domain.
 54    maxItems: 1
 55
 56  required-opps:
 57    description:
 58      A phandle to an OPP node describing required MMCX performance point.
 59    maxItems: 1
 60
 61required:
 62  - compatible
 63  - clocks
 64  - '#power-domain-cells'
 65
 66allOf:
 67  - $ref: qcom,gcc.yaml#
 68
 69unevaluatedProperties: false
 70
 71examples:
 72  - |
 73    #include <dt-bindings/clock/qcom,sm8550-gcc.h>
 74    #include <dt-bindings/clock/qcom,rpmh.h>
 75    #include <dt-bindings/power/qcom,rpmhpd.h>
 76    clock-controller@af00000 {
 77      compatible = "qcom,sm8550-dispcc";
 78      reg = <0x0af00000 0x10000>;
 79      clocks = <&rpmhcc RPMH_CXO_CLK>,
 80               <&rpmhcc RPMH_CXO_CLK_A>,
 81               <&gcc GCC_DISP_AHB_CLK>,
 82               <&sleep_clk>,
 83               <&dsi0_phy 0>,
 84               <&dsi0_phy 1>,
 85               <&dsi1_phy 0>,
 86               <&dsi1_phy 1>,
 87               <&dp0_phy 0>,
 88               <&dp0_phy 1>,
 89               <&dp1_phy 0>,
 90               <&dp1_phy 1>,
 91               <&dp2_phy 0>,
 92               <&dp2_phy 1>,
 93               <&dp3_phy 0>,
 94               <&dp3_phy 1>;
 95      #clock-cells = <1>;
 96      #reset-cells = <1>;
 97      #power-domain-cells = <1>;
 98      power-domains = <&rpmhpd RPMHPD_MMCX>;
 99      required-opps = <&rpmhpd_opp_low_svs>;
100    };
101...