qcom,ipq9574-nsscc.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424
  8
  9maintainers:
 10  - Bjorn Andersson <andersson@kernel.org>
 11  - Anusha Rao <quic_anusha@quicinc.com>
 12
 13description: |
 14  Qualcomm networking sub system clock control module provides the clocks,
 15  resets on IPQ9574 and IPQ5424
 16
 17  See also:
 18    include/dt-bindings/clock/qcom,ipq5424-nsscc.h
 19    include/dt-bindings/clock/qcom,ipq9574-nsscc.h
 20    include/dt-bindings/reset/qcom,ipq5424-nsscc.h
 21    include/dt-bindings/reset/qcom,ipq9574-nsscc.h
 22
 23properties:
 24  compatible:
 25    enum:
 26      - qcom,ipq5424-nsscc
 27      - qcom,ipq9574-nsscc
 28
 29  clocks:
 30    items:
 31      - description: Board XO source
 32      - description: CMN_PLL NSS (Bias PLL cc) clock source. This clock rate
 33          can vary for different IPQ SoCs. For example, it is 1200 MHz on the
 34          IPQ9574 and 300 MHz on the IPQ5424.
 35      - description: CMN_PLL PPE (Bias PLL ubi nc) clock source. The clock
 36          rate can vary for different IPQ SoCs. For example, it is 353 MHz
 37          on the IPQ9574 and 375 MHz on the IPQ5424.
 38      - description: GCC GPLL0 OUT AUX clock source
 39      - description: Uniphy0 NSS Rx clock source
 40      - description: Uniphy0 NSS Tx clock source
 41      - description: Uniphy1 NSS Rx clock source
 42      - description: Uniphy1 NSS Tx clock source
 43      - description: Uniphy2 NSS Rx clock source
 44      - description: Uniphy2 NSS Tx clock source
 45      - description: GCC NSSCC clock source
 46
 47  '#interconnect-cells':
 48    const: 1
 49
 50  clock-names:
 51    items:
 52      - const: xo
 53      - enum:
 54          - nss_1200
 55          - nss
 56      - enum:
 57          - ppe_353
 58          - ppe
 59      - const: gpll0_out
 60      - const: uniphy0_rx
 61      - const: uniphy0_tx
 62      - const: uniphy1_rx
 63      - const: uniphy1_tx
 64      - const: uniphy2_rx
 65      - const: uniphy2_tx
 66      - const: bus
 67
 68required:
 69  - compatible
 70  - clocks
 71  - clock-names
 72
 73allOf:
 74  - $ref: qcom,gcc.yaml#
 75  - if:
 76      properties:
 77        compatible:
 78          const: qcom,ipq9574-nsscc
 79    then:
 80      properties:
 81        clock-names:
 82          items:
 83            - const: xo
 84            - const: nss_1200
 85            - const: ppe_353
 86            - const: gpll0_out
 87            - const: uniphy0_rx
 88            - const: uniphy0_tx
 89            - const: uniphy1_rx
 90            - const: uniphy1_tx
 91            - const: uniphy2_rx
 92            - const: uniphy2_tx
 93            - const: bus
 94    else:
 95      properties:
 96        clock-names:
 97          items:
 98            - const: xo
 99            - const: nss
100            - const: ppe
101            - const: gpll0_out
102            - const: uniphy0_rx
103            - const: uniphy0_tx
104            - const: uniphy1_rx
105            - const: uniphy1_tx
106            - const: uniphy2_rx
107            - const: uniphy2_tx
108            - const: bus
109
110unevaluatedProperties: false
111
112examples:
113  - |
114    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
115    #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
116    clock-controller@39b00000 {
117      compatible = "qcom,ipq9574-nsscc";
118      reg = <0x39b00000 0x80000>;
119      clocks = <&xo_board_clk>,
120               <&cmn_pll NSS_1200MHZ_CLK>,
121               <&cmn_pll PPE_353MHZ_CLK>,
122               <&gcc GPLL0_OUT_AUX>,
123               <&uniphy 0>,
124               <&uniphy 1>,
125               <&uniphy 2>,
126               <&uniphy 3>,
127               <&uniphy 4>,
128               <&uniphy 5>,
129               <&gcc GCC_NSSCC_CLK>;
130      clock-names = "xo",
131                    "nss_1200",
132                    "ppe_353",
133                    "gpll0_out",
134                    "uniphy0_rx",
135                    "uniphy0_tx",
136                    "uniphy1_rx",
137                    "uniphy1_tx",
138                    "uniphy2_rx",
139                    "uniphy2_tx",
140                    "bus";
141      #clock-cells = <1>;
142      #reset-cells = <1>;
143      #interconnect-cells = <1>;
144    };
145...