qcom,glymur-gcc.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Global Clock & Reset Controller on Glymur SoC
  8
  9maintainers:
 10  - Taniya Das <taniya.das@oss.qualcomm.com>
 11
 12description: |
 13  Qualcomm global clock control module provides the clocks, resets and power
 14  domains on Glymur SoC.
 15
 16  See also: include/dt-bindings/clock/qcom,glymur-gcc.h
 17
 18properties:
 19  compatible:
 20    const: qcom,glymur-gcc
 21
 22  clocks:
 23    items:
 24      - description: Board XO source
 25      - description: Board XO_A source
 26      - description: Sleep clock source
 27      - description: USB 0 Phy DP0 GMUX clock source
 28      - description: USB 0 Phy DP1 GMUX clock source
 29      - description: USB 0 Phy PCIE PIPEGMUX clock source
 30      - description: USB 0 Phy PIPEGMUX clock source
 31      - description: USB 0 Phy SYS PCIE PIPEGMUX clock source
 32      - description: USB 1 Phy DP0 GMUX 2 clock source
 33      - description: USB 1 Phy DP1 GMUX 2 clock source
 34      - description: USB 1 Phy PCIE PIPEGMUX clock source
 35      - description: USB 1 Phy PIPEGMUX clock source
 36      - description: USB 1 Phy SYS PCIE PIPEGMUX clock source
 37      - description: USB 2 Phy DP0 GMUX 2 clock source
 38      - description: USB 2 Phy DP1 GMUX 2 clock source
 39      - description: USB 2 Phy PCIE PIPEGMUX clock source
 40      - description: USB 2 Phy PIPEGMUX clock source
 41      - description: USB 2 Phy SYS PCIE PIPEGMUX clock source
 42      - description: PCIe 3a pipe clock
 43      - description: PCIe 3b pipe clock
 44      - description: PCIe 4 pipe clock
 45      - description: PCIe 5 pipe clock
 46      - description: PCIe 6 pipe clock
 47      - description: QUSB4 0 PHY RX 0 clock source
 48      - description: QUSB4 0 PHY RX 1 clock source
 49      - description: QUSB4 1 PHY RX 0 clock source
 50      - description: QUSB4 1 PHY RX 1 clock source
 51      - description: QUSB4 2 PHY RX 0 clock source
 52      - description: QUSB4 2 PHY RX 1 clock source
 53      - description: UFS PHY RX Symbol 0 clock source
 54      - description: UFS PHY RX Symbol 1 clock source
 55      - description: UFS PHY TX Symbol 0 clock source
 56      - description: USB3 PHY 0 pipe clock source
 57      - description: USB3 PHY 1 pipe clock source
 58      - description: USB3 PHY 2 pipe clock source
 59      - description: USB3 UNI PHY pipe 0 clock source
 60      - description: USB3 UNI PHY pipe 1 clock source
 61      - description: USB4 PHY 0 pcie pipe clock source
 62      - description: USB4 PHY 0 Max pipe clock source
 63      - description: USB4 PHY 1 pcie pipe clock source
 64      - description: USB4 PHY 1 Max pipe clock source
 65      - description: USB4 PHY 2 pcie pipe clock source
 66      - description: USB4 PHY 2 Max pipe clock source
 67
 68required:
 69  - compatible
 70  - clocks
 71  - '#power-domain-cells'
 72
 73allOf:
 74  - $ref: qcom,gcc.yaml#
 75
 76unevaluatedProperties: false
 77
 78examples:
 79  - |
 80    #include <dt-bindings/clock/qcom,rpmh.h>
 81    clock-controller@100000 {
 82      compatible = "qcom,glymur-gcc";
 83      reg = <0x100000 0x1f9000>;
 84      clocks = <&rpmhcc RPMH_CXO_CLK>,
 85               <&rpmhcc RPMH_CXO_CLK_A>,
 86               <&sleep_clk>,
 87               <&usb_0_phy_dp0_gmux>,
 88               <&usb_0_phy_dp1_gmux>,
 89               <&usb_0_phy_pcie_pipegmux>,
 90               <&usb_0_phy_pipegmux>,
 91               <&usb_0_phy_sys_pcie_pipegmux>,
 92               <&usb_1_phy_dp0_gmux_2>,
 93               <&usb_1_phy_dp1_gmux_2>,
 94               <&usb_1_phy_pcie_pipegmux>,
 95               <&usb_1_phy_pipegmux>,
 96               <&usb_1_phy_sys_pcie_pipegmux>,
 97               <&usb_2_phy_dp0_gmux 2>,
 98               <&usb_2_phy_dp1_gmux 2>,
 99               <&usb_2_phy_pcie_pipegmux>,
100               <&usb_2_phy_pipegmux>,
101               <&usb_2_phy_sys_pcie_pipegmux>,
102               <&pcie_3a_pipe>, <&pcie_3b_pipe>,
103               <&pcie_4_pipe>, <&pcie_5_pipe>,
104               <&pcie_6_pipe>,
105               <&qusb4_0_phy_rx_0>, <&qusb4_0_phy_rx_1>,
106               <&qusb4_1_phy_rx_0>, <&qusb4_1_phy_rx_1>,
107               <&qusb4_2_phy_rx_0>, <&qusb4_2_phy_rx_1>,
108               <&ufs_phy_rx_symbol_0>, <&ufs_phy_rx_symbol_1>,
109               <&ufs_phy_tx_symbol_0>,
110               <&usb3_phy_0_pipe>, <&usb3_phy_1_pipe>,
111               <&usb3_phy_2_pipe>,
112               <&usb3_uni_phy_pipe_0>, <&usb3_uni_phy_pipe_1>,
113               <&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>,
114               <&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>,
115               <&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>;
116      #clock-cells = <1>;
117      #reset-cells = <1>;
118      #power-domain-cells = <1>;
119    };
120
121...