mediatek,mt8196-clock.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: MediaTek Functional Clock Controller for MT8196
  8
  9maintainers:
 10  - Guangjie Song <guangjie.song@mediatek.com>
 11  - Laura Nao <laura.nao@collabora.com>
 12
 13description: |
 14  The clock architecture in MediaTek SoCs is structured like below:
 15  PLLs -->
 16          dividers -->
 17                      muxes
 18                           -->
 19                              clock gate
 20
 21  The device nodes provide clock gate control in different IP blocks.
 22
 23properties:
 24  compatible:
 25    items:
 26      - enum:
 27          - mediatek,mt8196-imp-iic-wrap-c
 28          - mediatek,mt8196-imp-iic-wrap-e
 29          - mediatek,mt8196-imp-iic-wrap-n
 30          - mediatek,mt8196-imp-iic-wrap-w
 31          - mediatek,mt8196-mdpsys0
 32          - mediatek,mt8196-mdpsys1
 33          - mediatek,mt8196-pericfg-ao
 34          - mediatek,mt8196-pextp0cfg-ao
 35          - mediatek,mt8196-pextp1cfg-ao
 36          - mediatek,mt8196-ufscfg-ao
 37          - mediatek,mt8196-vencsys
 38          - mediatek,mt8196-vencsys-c1
 39          - mediatek,mt8196-vencsys-c2
 40          - mediatek,mt8196-vdecsys
 41          - mediatek,mt8196-vdecsys-soc
 42          - mediatek,mt8196-vdisp-ao
 43      - const: syscon
 44
 45  reg:
 46    maxItems: 1
 47
 48  '#clock-cells':
 49    const: 1
 50
 51  '#reset-cells':
 52    const: 1
 53    description:
 54      Reset lines for PEXTP0/1 and UFS blocks.
 55
 56  mediatek,hardware-voter:
 57    $ref: /schemas/types.yaml#/definitions/phandle
 58    description: |
 59      Phandle to the "Hardware Voter" (HWV), as named in the vendor
 60      documentation for MT8196/MT6991.
 61
 62      The HWV is a SoC-internal fixed-function MCU used to collect votes from
 63      both the Application Processor and other remote processors within the SoC.
 64      It is intended to transparently enable or disable hardware resources (such
 65      as power domains or clocks) based on internal vote aggregation handled by
 66      the MCU's internal state machine.
 67
 68      However, in practice, this design is incomplete. While the HWV performs
 69      some internal vote aggregation,software is still required to
 70      - Manually enable power supplies externally, if present and if required
 71      - Manually enable parent clocks via direct MMIO writes to clock controllers
 72      - Enable the FENC after the clock has been ungated via direct MMIO
 73      writes to clock controllers
 74
 75      As such, the HWV behaves more like a hardware-managed clock reference
 76      counter than a true voter. Furthermore, it is not a separate
 77      controller. It merely serves as an alternative interface to the same
 78      underlying clock or power controller. Actual control still requires
 79      direct access to the controller's own MMIO register space, in
 80      addition to writing to the HWV's MMIO region.
 81
 82      For this reason, a custom phandle is used here - drivers need to directly
 83      access the HWV MMIO region in a syscon-like fashion, due to how the
 84      hardware is wired. This differs from true hardware voting systems, which
 85      typically do not require custom phandles and rely instead on generic APIs
 86      (clocks, power domains, interconnects).
 87
 88      The name "hardware-voter" is retained to match vendor documentation, but
 89      this should not be reused or misunderstood as a proper voting mechanism.
 90
 91required:
 92  - compatible
 93  - reg
 94  - '#clock-cells'
 95
 96additionalProperties: false
 97
 98examples:
 99  - |
100    pericfg_ao: clock-controller@16640000 {
101        compatible = "mediatek,mt8196-pericfg-ao", "syscon";
102        reg = <0x16640000 0x1000>;
103        mediatek,hardware-voter = <&scp_hwv>;
104        #clock-cells = <1>;
105    };
106  - |
107    pextp0cfg_ao: clock-controller@169b0000 {
108        compatible = "mediatek,mt8196-pextp0cfg-ao", "syscon";
109        reg = <0x169b0000 0x1000>;
110        #clock-cells = <1>;
111        #reset-cells = <1>;
112    };