img,pistachio-clk.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/clock/img,pistachio-clk.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Imagination Technologies Pistachio SoC clock controllers
  8
  9maintainers:
 10  - Andrew Bresticker <abrestic@chromium.org>
 11
 12description: |
 13  Pistachio has four clock controllers (core clock, peripheral clock, peripheral
 14  general control, and top general control) which are instantiated individually
 15  from the device-tree.
 16
 17  Core clock controller:
 18
 19  The core clock controller generates clocks for the CPU, RPU (WiFi + BT
 20  co-processor), audio, and several peripherals.
 21
 22  Peripheral clock controller:
 23
 24  The peripheral clock controller generates clocks for the DDR, ROM, and other
 25  peripherals. The peripheral system clock ("periph_sys") generated by the core
 26  clock controller is the input clock to the peripheral clock controller.
 27
 28  Peripheral general control:
 29
 30  The peripheral general control block generates system interface clocks and
 31  resets for various peripherals. It also contains miscellaneous peripheral
 32  control registers.
 33
 34  Top-level general control:
 35
 36  The top-level general control block contains miscellaneous control registers
 37  and gates for the external clocks "audio_clk_in" and "enet_clk_in".
 38
 39properties:
 40  compatible:
 41    items:
 42      - enum:
 43          - img,pistachio-clk
 44          - img,pistachio-clk-periph
 45          - img,pistachio-cr-periph
 46          - img,pistachio-cr-top
 47
 48  reg:
 49    maxItems: 1
 50
 51  '#clock-cells':
 52    const: 1
 53
 54  clocks:
 55    minItems: 1
 56    maxItems: 3
 57
 58  clock-names:
 59    minItems: 1
 60    maxItems: 3
 61
 62required:
 63  - compatible
 64  - reg
 65  - '#clock-cells'
 66  - clocks
 67  - clock-names
 68
 69allOf:
 70  - if:
 71      properties:
 72        compatible:
 73          contains:
 74            const: img,pistachio-clk
 75    then:
 76      properties:
 77        clocks:
 78          items:
 79            - description: External 52Mhz oscillator
 80            - description: Alternate audio reference clock
 81            - description: Alternate ethernet PHY clock
 82
 83        clock-names:
 84          items:
 85            - const: xtal
 86            - const: audio_refclk_ext_gate
 87            - const: ext_enet_in_gate
 88
 89  - if:
 90      properties:
 91        compatible:
 92          contains:
 93            const: img,pistachio-clk-periph
 94    then:
 95      properties:
 96        clocks:
 97          items:
 98            - description: Peripheral system clock
 99
100        clock-names:
101          items:
102            - const: periph_sys_core
103
104  - if:
105      properties:
106        compatible:
107          contains:
108            const: img,pistachio-cr-periph
109    then:
110      properties:
111        clocks:
112          items:
113            - description: System interface clock
114
115        clock-names:
116          items:
117            - const: sys
118
119  - if:
120      properties:
121        compatible:
122          contains:
123            const: img,pistachio-cr-top
124    then:
125      properties:
126        clocks:
127          items:
128            - description: External audio reference clock
129            - description: External ethernet PHY clock
130
131        clock-names:
132          items:
133            - const: audio_clk_in
134            - const: enet_clk_in
135
136additionalProperties: false