fsl,imx8-acm.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: NXP i.MX8 Audio Clock Mux
  8
  9maintainers:
 10  - Shengjiu Wang <shengjiu.wang@nxp.com>
 11
 12description: |
 13  NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP
 14  used to control Audio related clock on the SoC.
 15
 16properties:
 17  compatible:
 18    enum:
 19      - fsl,imx8dxl-acm
 20      - fsl,imx8qm-acm
 21      - fsl,imx8qxp-acm
 22
 23  reg:
 24    maxItems: 1
 25
 26  power-domains:
 27    minItems: 13
 28    maxItems: 21
 29
 30  '#clock-cells':
 31    const: 1
 32    description:
 33      The clock consumer should specify the desired clock by having the clock
 34      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h
 35      for the full list of i.MX8 ACM clock IDs.
 36
 37  clocks:
 38    minItems: 13
 39    maxItems: 27
 40
 41  clock-names:
 42    minItems: 13
 43    maxItems: 27
 44
 45required:
 46  - compatible
 47  - reg
 48  - power-domains
 49  - '#clock-cells'
 50  - clocks
 51  - clock-names
 52
 53allOf:
 54  - if:
 55      properties:
 56        compatible:
 57          contains:
 58            enum:
 59              - fsl,imx8qxp-acm
 60    then:
 61      properties:
 62        power-domains:
 63          items:
 64            - description: power domain of IMX_SC_R_AUDIO_CLK_0
 65            - description: power domain of IMX_SC_R_AUDIO_CLK_1
 66            - description: power domain of IMX_SC_R_MCLK_OUT_0
 67            - description: power domain of IMX_SC_R_MCLK_OUT_1
 68            - description: power domain of IMX_SC_R_AUDIO_PLL_0
 69            - description: power domain of IMX_SC_R_AUDIO_PLL_1
 70            - description: power domain of IMX_SC_R_ASRC_0
 71            - description: power domain of IMX_SC_R_ASRC_1
 72            - description: power domain of IMX_SC_R_ESAI_0
 73            - description: power domain of IMX_SC_R_SAI_0
 74            - description: power domain of IMX_SC_R_SAI_1
 75            - description: power domain of IMX_SC_R_SAI_2
 76            - description: power domain of IMX_SC_R_SAI_3
 77            - description: power domain of IMX_SC_R_SAI_4
 78            - description: power domain of IMX_SC_R_SAI_5
 79            - description: power domain of IMX_SC_R_SPDIF_0
 80            - description: power domain of IMX_SC_R_MQS_0
 81
 82        clocks:
 83          minItems: 18
 84          maxItems: 18
 85
 86        clock-names:
 87          items:
 88            - const: aud_rec_clk0_lpcg_clk
 89            - const: aud_rec_clk1_lpcg_clk
 90            - const: aud_pll_div_clk0_lpcg_clk
 91            - const: aud_pll_div_clk1_lpcg_clk
 92            - const: ext_aud_mclk0
 93            - const: ext_aud_mclk1
 94            - const: esai0_rx_clk
 95            - const: esai0_rx_hf_clk
 96            - const: esai0_tx_clk
 97            - const: esai0_tx_hf_clk
 98            - const: spdif0_rx
 99            - const: sai0_rx_bclk
100            - const: sai0_tx_bclk
101            - const: sai1_rx_bclk
102            - const: sai1_tx_bclk
103            - const: sai2_rx_bclk
104            - const: sai3_rx_bclk
105            - const: sai4_rx_bclk
106
107  - if:
108      properties:
109        compatible:
110          contains:
111            enum:
112              - fsl,imx8qm-acm
113    then:
114      properties:
115        power-domains:
116          items:
117            - description: power domain of IMX_SC_R_AUDIO_CLK_0
118            - description: power domain of IMX_SC_R_AUDIO_CLK_1
119            - description: power domain of IMX_SC_R_MCLK_OUT_0
120            - description: power domain of IMX_SC_R_MCLK_OUT_1
121            - description: power domain of IMX_SC_R_AUDIO_PLL_0
122            - description: power domain of IMX_SC_R_AUDIO_PLL_1
123            - description: power domain of IMX_SC_R_ASRC_0
124            - description: power domain of IMX_SC_R_ASRC_1
125            - description: power domain of IMX_SC_R_ESAI_0
126            - description: power domain of IMX_SC_R_ESAI_1
127            - description: power domain of IMX_SC_R_SAI_0
128            - description: power domain of IMX_SC_R_SAI_1
129            - description: power domain of IMX_SC_R_SAI_2
130            - description: power domain of IMX_SC_R_SAI_3
131            - description: power domain of IMX_SC_R_SAI_4
132            - description: power domain of IMX_SC_R_SAI_5
133            - description: power domain of IMX_SC_R_SAI_6
134            - description: power domain of IMX_SC_R_SAI_7
135            - description: power domain of IMX_SC_R_SPDIF_0
136            - description: power domain of IMX_SC_R_SPDIF_1
137            - description: power domain of IMX_SC_R_MQS_0
138
139        clocks:
140          minItems: 27
141          maxItems: 27
142
143        clock-names:
144          items:
145            - const: aud_rec_clk0_lpcg_clk
146            - const: aud_rec_clk1_lpcg_clk
147            - const: aud_pll_div_clk0_lpcg_clk
148            - const: aud_pll_div_clk1_lpcg_clk
149            - const: mlb_clk
150            - const: hdmi_rx_mclk
151            - const: ext_aud_mclk0
152            - const: ext_aud_mclk1
153            - const: esai0_rx_clk
154            - const: esai0_rx_hf_clk
155            - const: esai0_tx_clk
156            - const: esai0_tx_hf_clk
157            - const: esai1_rx_clk
158            - const: esai1_rx_hf_clk
159            - const: esai1_tx_clk
160            - const: esai1_tx_hf_clk
161            - const: spdif0_rx
162            - const: spdif1_rx
163            - const: sai0_rx_bclk
164            - const: sai0_tx_bclk
165            - const: sai1_rx_bclk
166            - const: sai1_tx_bclk
167            - const: sai2_rx_bclk
168            - const: sai3_rx_bclk
169            - const: sai4_rx_bclk
170            - const: sai5_tx_bclk
171            - const: sai6_rx_bclk
172
173  - if:
174      properties:
175        compatible:
176          contains:
177            enum:
178              - fsl,imx8dxl-acm
179    then:
180      properties:
181        power-domains:
182          items:
183            - description: power domain of IMX_SC_R_AUDIO_CLK_0
184            - description: power domain of IMX_SC_R_AUDIO_CLK_1
185            - description: power domain of IMX_SC_R_MCLK_OUT_0
186            - description: power domain of IMX_SC_R_MCLK_OUT_1
187            - description: power domain of IMX_SC_R_AUDIO_PLL_0
188            - description: power domain of IMX_SC_R_AUDIO_PLL_1
189            - description: power domain of IMX_SC_R_ASRC_0
190            - description: power domain of IMX_SC_R_SAI_0
191            - description: power domain of IMX_SC_R_SAI_1
192            - description: power domain of IMX_SC_R_SAI_2
193            - description: power domain of IMX_SC_R_SAI_3
194            - description: power domain of IMX_SC_R_SPDIF_0
195            - description: power domain of IMX_SC_R_MQS_0
196
197        clocks:
198          minItems: 13
199          maxItems: 13
200
201        clock-names:
202          items:
203            - const: aud_rec_clk0_lpcg_clk
204            - const: aud_rec_clk1_lpcg_clk
205            - const: aud_pll_div_clk0_lpcg_clk
206            - const: aud_pll_div_clk1_lpcg_clk
207            - const: ext_aud_mclk0
208            - const: ext_aud_mclk1
209            - const: spdif0_rx
210            - const: sai0_rx_bclk
211            - const: sai0_tx_bclk
212            - const: sai1_rx_bclk
213            - const: sai1_tx_bclk
214            - const: sai2_rx_bclk
215            - const: sai3_rx_bclk
216
217additionalProperties: false
218
219examples:
220  # Clock Control Module node:
221  - |
222    #include <dt-bindings/clock/imx8-lpcg.h>
223    #include <dt-bindings/firmware/imx/rsrc.h>
224
225    clock-controller@59e00000 {
226        compatible = "fsl,imx8qxp-acm";
227        reg = <0x59e00000 0x1d0000>;
228        #clock-cells = <1>;
229        power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
230                        <&pd IMX_SC_R_AUDIO_CLK_1>,
231                        <&pd IMX_SC_R_MCLK_OUT_0>,
232                        <&pd IMX_SC_R_MCLK_OUT_1>,
233                        <&pd IMX_SC_R_AUDIO_PLL_0>,
234                        <&pd IMX_SC_R_AUDIO_PLL_1>,
235                        <&pd IMX_SC_R_ASRC_0>,
236                        <&pd IMX_SC_R_ASRC_1>,
237                        <&pd IMX_SC_R_ESAI_0>,
238                        <&pd IMX_SC_R_SAI_0>,
239                        <&pd IMX_SC_R_SAI_1>,
240                        <&pd IMX_SC_R_SAI_2>,
241                        <&pd IMX_SC_R_SAI_3>,
242                        <&pd IMX_SC_R_SAI_4>,
243                        <&pd IMX_SC_R_SAI_5>,
244                        <&pd IMX_SC_R_SPDIF_0>,
245                        <&pd IMX_SC_R_MQS_0>;
246        clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,
247                 <&aud_rec1_lpcg IMX_LPCG_CLK_0>,
248                 <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
249                 <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
250                 <&clk_ext_aud_mclk0>,
251                 <&clk_ext_aud_mclk1>,
252                 <&clk_esai0_rx_clk>,
253                 <&clk_esai0_rx_hf_clk>,
254                 <&clk_esai0_tx_clk>,
255                 <&clk_esai0_tx_hf_clk>,
256                 <&clk_spdif0_rx>,
257                 <&clk_sai0_rx_bclk>,
258                 <&clk_sai0_tx_bclk>,
259                 <&clk_sai1_rx_bclk>,
260                 <&clk_sai1_tx_bclk>,
261                 <&clk_sai2_rx_bclk>,
262                 <&clk_sai3_rx_bclk>,
263                 <&clk_sai4_rx_bclk>;
264        clock-names = "aud_rec_clk0_lpcg_clk",
265                      "aud_rec_clk1_lpcg_clk",
266                      "aud_pll_div_clk0_lpcg_clk",
267                      "aud_pll_div_clk1_lpcg_clk",
268                      "ext_aud_mclk0",
269                      "ext_aud_mclk1",
270                      "esai0_rx_clk",
271                      "esai0_rx_hf_clk",
272                      "esai0_tx_clk",
273                      "esai0_tx_hf_clk",
274                      "spdif0_rx",
275                      "sai0_rx_bclk",
276                      "sai0_tx_bclk",
277                      "sai1_rx_bclk",
278                      "sai1_tx_bclk",
279                      "sai2_rx_bclk",
280                      "sai3_rx_bclk",
281                      "sai4_rx_bclk";
282    };