amlogic,c3-peripherals-clkc.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
  3%YAML 1.2
  4---
  5$id: http://devicetree.org/schemas/clock/amlogic,c3-peripherals-clkc.yaml#
  6$schema: http://devicetree.org/meta-schemas/core.yaml#
  7
  8title: Amlogic C3 series Peripheral Clock Controller
  9
 10maintainers:
 11  - Neil Armstrong <neil.armstrong@linaro.org>
 12  - Jerome Brunet <jbrunet@baylibre.com>
 13  - Xianwei Zhao <xianwei.zhao@amlogic.com>
 14  - Chuan Liu <chuan.liu@amlogic.com>
 15
 16properties:
 17  compatible:
 18    const: amlogic,c3-peripherals-clkc
 19
 20  reg:
 21    maxItems: 1
 22
 23  clocks:
 24    minItems: 16
 25    items:
 26      - description: input oscillator (usually at 24MHz)
 27      - description: input oscillators multiplexer
 28      - description: input fix pll
 29      - description: input fclk div 2
 30      - description: input fclk div 2p5
 31      - description: input fclk div 3
 32      - description: input fclk div 4
 33      - description: input fclk div 5
 34      - description: input fclk div 7
 35      - description: input gp0 pll
 36      - description: input gp1 pll
 37      - description: input hifi pll
 38      - description: input sys clk
 39      - description: input axi clk
 40      - description: input sys pll div 16
 41      - description: input cpu clk div 16
 42      - description: input pad clock for rtc clk (optional)
 43
 44  clock-names:
 45    minItems: 16
 46    items:
 47      - const: xtal_24m
 48      - const: oscin
 49      - const: fix
 50      - const: fdiv2
 51      - const: fdiv2p5
 52      - const: fdiv3
 53      - const: fdiv4
 54      - const: fdiv5
 55      - const: fdiv7
 56      - const: gp0
 57      - const: gp1
 58      - const: hifi
 59      - const: sysclk
 60      - const: axiclk
 61      - const: sysplldiv16
 62      - const: cpudiv16
 63      - const: pad_osc
 64
 65  "#clock-cells":
 66    const: 1
 67
 68required:
 69  - compatible
 70  - reg
 71  - clocks
 72  - clock-names
 73  - "#clock-cells"
 74
 75additionalProperties: false
 76
 77examples:
 78  - |
 79    apb {
 80        #address-cells = <2>;
 81        #size-cells = <2>;
 82
 83        clock-controller@0 {
 84            compatible = "amlogic,c3-peripherals-clkc";
 85            reg = <0x0 0x0 0x0 0x49c>;
 86            #clock-cells = <1>;
 87            clocks = <&xtal_24m>,
 88                     <&scmi_clk 8>,
 89                     <&scmi_clk 12>,
 90                     <&clkc_pll 3>,
 91                     <&clkc_pll 5>,
 92                     <&clkc_pll 7>,
 93                     <&clkc_pll 9>,
 94                     <&clkc_pll 11>,
 95                     <&clkc_pll 13>,
 96                     <&clkc_pll 15>,
 97                     <&scmi_clk 13>,
 98                     <&clkc_pll 17>,
 99                     <&scmi_clk 9>,
100                     <&scmi_clk 10>,
101                     <&scmi_clk 14>,
102                     <&scmi_clk 15>;
103            clock-names = "xtal_24m",
104                          "oscin",
105                          "fix",
106                          "fdiv2",
107                          "fdiv2p5",
108                          "fdiv3",
109                          "fdiv4",
110                          "fdiv5",
111                          "fdiv7",
112                          "gp0",
113                          "gp1",
114                          "hifi",
115                          "sysclk",
116                          "axiclk",
117                          "sysplldiv16",
118                          "cpudiv16";
119        };
120    };