adi,axi-clkgen.yaml

 1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 2%YAML 1.2
 3---
 4$id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
 5$schema: http://devicetree.org/meta-schemas/core.yaml#
 6
 7title: Analog Devices AXI clkgen pcore clock generator
 8
 9maintainers:
10  - Lars-Peter Clausen <lars@metafoo.de>
11  - Michael Hennerich <michael.hennerich@analog.com>
12
13description: |
14  The axi_clkgen IP core is a software programmable clock generator,
15  that can be synthesized on various FPGA platforms.
16
17  Link: https://wiki.analog.com/resources/fpga/docs/axi_clkgen
18
19properties:
20  compatible:
21    enum:
22      - adi,axi-clkgen-2.00.a
23      - adi,zynqmp-axi-clkgen-2.00.a
24
25  clocks:
26    description:
27      Specifies the reference clock(s) from which the output frequency is
28      derived. This must either reference one clock if only the first clock
29      input is connected or two if both clock inputs are connected. The last
30      clock is the AXI bus clock that needs to be enabled so we can access the
31      core registers.
32    minItems: 2
33    maxItems: 3
34
35  clock-names:
36    oneOf:
37      - items:
38          - const: clkin1
39          - const: s_axi_aclk
40      - items:
41          - const: clkin1
42          - const: clkin2
43          - const: s_axi_aclk
44
45  clock-output-names:
46    maxItems: 1
47
48  '#clock-cells':
49    const: 0
50
51  reg:
52    maxItems: 1
53
54required:
55  - compatible
56  - reg
57  - clocks
58  - clock-names
59  - '#clock-cells'
60
61additionalProperties: false
62
63examples:
64  - |
65    clock-controller@ff000000 {
66      compatible = "adi,axi-clkgen-2.00.a";
67      #clock-cells = <0>;
68      reg = <0xff000000 0x1000>;
69      clocks = <&osc 1>, <&clkc 15>;
70      clock-names = "clkin1", "s_axi_aclk";
71      clock-output-names = "spi_sclk";
72    };