l2c2x0.yaml

  1# SPDX-License-Identifier: GPL-2.0
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/cache/l2c2x0.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: ARM L2 Cache Controller
  8
  9maintainers:
 10  - Rob Herring <robh@kernel.org>
 11
 12description: |+
 13  ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/
 14  PL220/PL310 and variants) based level 2 cache controller. All these various
 15  implementations of the L2 cache controller have compatible programming
 16  models (Note 1). Some of the properties that are just prefixed "cache-*" are
 17  taken from section 3.7.3 of the Devicetree Specification which can be found
 18  at:
 19  https://www.devicetree.org/specifications/
 20
 21  Note 1: The description in this document doesn't apply to integrated L2
 22    cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
 23    integrated L2 controllers are assumed to be all preconfigured by
 24    early secure boot code. Thus no need to deal with their configuration
 25    in the kernel at all.
 26
 27allOf:
 28  - $ref: /schemas/cache-controller.yaml#
 29
 30properties:
 31  compatible:
 32    oneOf:
 33      - enum:
 34          - arm,pl310-cache
 35          - arm,l220-cache
 36          - arm,l210-cache
 37            # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
 38          - bcm,bcm11351-a2-pl310-cache
 39            # For Broadcom bcm11351 chipset where an
 40            # offset needs to be added to the address before passing down to the L2
 41            # cache controller
 42          - brcm,bcm11351-a2-pl310-cache
 43            # Marvell Controller designed to be
 44            # compatible with the ARM one, with system cache mode (meaning
 45            # maintenance operations on L1 are broadcasted to the L2 and L2
 46            # performs the same operation).
 47          - marvell,aurora-system-cache
 48            # Marvell Controller designed to be
 49            # compatible with the ARM one with outer cache mode.
 50          - marvell,aurora-outer-cache
 51      - items:
 52           # Marvell Tauros3 cache controller, compatible
 53           # with arm,pl310-cache controller.
 54          - const: marvell,tauros3-cache
 55          - const: arm,pl310-cache
 56
 57  cache-level:
 58    const: 2
 59
 60  cache-unified: true
 61  cache-size: true
 62  cache-sets: true
 63  cache-block-size: true
 64  cache-line-size: true
 65
 66  reg:
 67    maxItems: 1
 68
 69  arm,data-latency:
 70    description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
 71      read, write and setup latencies. Minimum valid values are 1. Controllers
 72      without setup latency control should use a value of 0.
 73    $ref: /schemas/types.yaml#/definitions/uint32-array
 74    minItems: 2
 75    maxItems: 3
 76    items:
 77      minimum: 0
 78      maximum: 8
 79
 80  arm,tag-latency:
 81    description: Cycles of latency for Tag RAM accesses. Specifies 3 cells of
 82      read, write and setup latencies. Controllers without setup latency control
 83      should use 0. Controllers without separate read and write Tag RAM latency
 84      values should only use the first cell.
 85    $ref: /schemas/types.yaml#/definitions/uint32-array
 86    minItems: 1
 87    maxItems: 3
 88    items:
 89      minimum: 0
 90      maximum: 8
 91
 92  arm,dirty-latency:
 93    description: Cycles of latency for Dirty RAMs. This is a single cell.
 94    $ref: /schemas/types.yaml#/definitions/uint32
 95    minimum: 1
 96    maximum: 8
 97
 98  arm,filter-ranges:
 99    description: <start length> Starting address and length of window to
100      filter. Addresses in the filter window are directed to the M1 port. Other
101      addresses will go to the M0 port.
102    $ref: /schemas/types.yaml#/definitions/uint32-array
103    minItems: 2
104    maxItems: 2
105
106  arm,io-coherent:
107    description: indicates that the system is operating in an hardware
108      I/O coherent mode. Valid only when the arm,pl310-cache compatible
109      string is used.
110    type: boolean
111
112  interrupts:
113    # Either a single combined interrupt or up to 9 individual interrupts
114    minItems: 1
115    maxItems: 9
116
117  cache-id-part:
118    description: cache id part number to be used if it is not present
119      on hardware
120    $ref: /schemas/types.yaml#/definitions/uint32
121
122  wt-override:
123    description: If present then L2 is forced to Write through mode
124    type: boolean
125
126  arm,double-linefill:
127    description: Override double linefill enable setting. Enable if
128      non-zero, disable if zero.
129    $ref: /schemas/types.yaml#/definitions/uint32
130    enum: [0, 1]
131
132  arm,double-linefill-incr:
133    description: Override double linefill on INCR read. Enable
134      if non-zero, disable if zero.
135    $ref: /schemas/types.yaml#/definitions/uint32
136    enum: [0, 1]
137
138  arm,double-linefill-wrap:
139    description: Override double linefill on WRAP read. Enable
140      if non-zero, disable if zero.
141    $ref: /schemas/types.yaml#/definitions/uint32
142    enum: [0, 1]
143
144  arm,prefetch-drop:
145    description: Override prefetch drop enable setting. Enable if non-zero,
146      disable if zero.
147    $ref: /schemas/types.yaml#/definitions/uint32
148    enum: [0, 1]
149
150  arm,prefetch-offset:
151    description: Override prefetch offset value.
152    $ref: /schemas/types.yaml#/definitions/uint32
153    enum: [0, 1, 2, 3, 4, 5, 6, 7, 15, 23, 31]
154
155  arm,shared-override:
156    description: The default behavior of the L220 or PL310 cache
157      controllers with respect to the shareable attribute is to transform "normal
158      memory non-cacheable transactions" into "cacheable no allocate" (for reads)
159      or "write through no write allocate" (for writes).
160      On systems where this may cause DMA buffer corruption, this property must
161      be specified to indicate that such transforms are precluded.
162    type: boolean
163
164  arm,parity-enable:
165    description: enable parity checking on the L2 cache (L220 or PL310).
166    type: boolean
167
168  arm,parity-disable:
169    description: disable parity checking on the L2 cache (L220 or PL310).
170    type: boolean
171
172  marvell,ecc-enable:
173    description: enable ECC protection on the L2 cache
174    type: boolean
175
176  arm,outer-sync-disable:
177    description: disable the outer sync operation on the L2 cache.
178      Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
179      will randomly hang unless outer sync operations are disabled.
180    type: boolean
181
182  prefetch-data:
183    description: |
184      Data prefetch. Value: <0> (forcibly disable), <1>
185      (forcibly enable), property absent (retain settings set by firmware)
186    $ref: /schemas/types.yaml#/definitions/uint32
187    enum: [0, 1]
188
189  prefetch-instr:
190    description: |
191      Instruction prefetch. Value: <0> (forcibly disable),
192      <1> (forcibly enable), property absent (retain settings set by
193      firmware)
194    $ref: /schemas/types.yaml#/definitions/uint32
195    enum: [0, 1]
196
197  arm,dynamic-clock-gating:
198    description: |
199      L2 dynamic clock gating. Value: <0> (forcibly
200      disable), <1> (forcibly enable), property absent (OS specific behavior,
201      preferably retain firmware settings)
202    $ref: /schemas/types.yaml#/definitions/uint32
203    enum: [0, 1]
204
205  arm,standby-mode:
206    description: L2 standby mode enable. Value <0> (forcibly disable),
207      <1> (forcibly enable), property absent (OS specific behavior,
208      preferably retain firmware settings)
209    $ref: /schemas/types.yaml#/definitions/uint32
210    enum: [0, 1]
211
212  arm,early-bresp-disable:
213    description: Disable the CA9 optimization Early BRESP (PL310)
214    type: boolean
215
216  arm,full-line-zero-disable:
217    description: Disable the CA9 optimization Full line of zero
218      write (PL310)
219    type: boolean
220
221required:
222  - compatible
223  - cache-unified
224  - reg
225
226additionalProperties: false
227
228examples:
229  - |
230    cache-controller@fff12000 {
231        compatible = "arm,pl310-cache";
232        reg = <0xfff12000 0x1000>;
233        arm,data-latency = <1 1 1>;
234        arm,tag-latency = <2 2 2>;
235        arm,filter-ranges = <0x80000000 0x8000000>;
236        cache-unified;
237        cache-level = <2>;
238        interrupts = <45>;
239    };
240
241...