andestech,ax45mp-cache.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2# Copyright (C) 2023 Renesas Electronics Corp.
  3%YAML 1.2
  4---
  5$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
  6$schema: http://devicetree.org/meta-schemas/core.yaml#
  7
  8title: Andestech AX45MP L2 Cache Controller
  9
 10maintainers:
 11  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 12
 13description:
 14  A level-2 cache (L2C) is used to improve the system performance by providing
 15  a large amount of cache line entries and reasonable access delays. The L2C
 16  is shared between cores, and a non-inclusive non-exclusive policy is used.
 17
 18select:
 19  properties:
 20    compatible:
 21      contains:
 22        enum:
 23          - andestech,ax45mp-cache
 24
 25  required:
 26    - compatible
 27
 28properties:
 29  compatible:
 30    items:
 31      - enum:
 32          - andestech,qilai-ax45mp-cache
 33          - renesas,r9a07g043f-ax45mp-cache
 34      - const: andestech,ax45mp-cache
 35      - const: cache
 36
 37  reg:
 38    maxItems: 1
 39
 40  interrupts:
 41    maxItems: 1
 42
 43  cache-line-size:
 44    const: 64
 45
 46  cache-level:
 47    const: 2
 48
 49  cache-sets:
 50    enum: [1024, 2048]
 51
 52  cache-size:
 53    enum: [131072, 262144, 524288, 1048576, 2097152]
 54
 55  cache-unified: true
 56
 57  next-level-cache: true
 58
 59additionalProperties: false
 60
 61required:
 62  - compatible
 63  - reg
 64  - interrupts
 65  - cache-line-size
 66  - cache-level
 67  - cache-sets
 68  - cache-size
 69  - cache-unified
 70
 71allOf:
 72  - if:
 73      properties:
 74        compatible:
 75          contains:
 76            const: andestech,qilai-ax45mp-cache
 77
 78    then:
 79      properties:
 80        cache-sets:
 81          const: 2048
 82        cache-size:
 83          const: 2097152
 84    else:
 85      properties:
 86        cache-sets:
 87          const: 1024
 88
 89examples:
 90  - |
 91    #include <dt-bindings/interrupt-controller/irq.h>
 92
 93    cache-controller@13400000 {
 94        compatible = "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cache",
 95                     "cache";
 96        reg = <0x13400000 0x100000>;
 97        interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
 98        cache-line-size = <64>;
 99        cache-level = <2>;
100        cache-sets = <1024>;
101        cache-size = <262144>;
102        cache-unified;
103    };