st,stm32mp25-rifsc.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: STM32 Resource isolation framework security controller
  8
  9maintainers:
 10  - Gatien Chevallier <gatien.chevallier@foss.st.com>
 11
 12description: |
 13  Resource isolation framework (RIF) is a comprehensive set of hardware blocks
 14  designed to enforce and manage isolation of STM32 hardware resources like
 15  memory and peripherals.
 16
 17  The RIFSC (RIF security controller) is composed of three sets of registers,
 18  each managing a specific set of hardware resources:
 19    - RISC registers associated with RISUP logic (resource isolation device unit
 20      for peripherals), assign all non-RIF aware peripherals to zero, one or
 21      any security domains (secure, privilege, compartment).
 22    - RIMC registers: associated with RIMU logic (resource isolation master
 23      unit), assign all non RIF-aware bus master to one security domain by
 24      setting secure, privileged and compartment information on the system bus.
 25      Alternatively, the RISUP logic controlling the device port access to a
 26      peripheral can assign target bus attributes to this peripheral master port
 27      (supported attribute: CID).
 28    - RISC registers associated with RISAL logic (resource isolation device unit
 29      for address space - Lite version), assign address space subregions to one
 30      security domains (secure, privilege, compartment).
 31
 32select:
 33  properties:
 34    compatible:
 35      contains:
 36        enum:
 37          - st,stm32mp21-rifsc
 38          - st,stm32mp25-rifsc
 39  required:
 40    - compatible
 41
 42properties:
 43  compatible:
 44    items:
 45      - enum:
 46          - st,stm32mp21-rifsc
 47          - st,stm32mp25-rifsc
 48      - const: simple-bus
 49
 50  reg:
 51    maxItems: 1
 52
 53  "#address-cells":
 54    const: 1
 55
 56  "#size-cells":
 57    const: 1
 58
 59  ranges: true
 60
 61  "#access-controller-cells":
 62    const: 1
 63    description:
 64      Contains the firewall ID associated to the peripheral.
 65
 66patternProperties:
 67  "@[0-9a-f]+$":
 68    description: Peripherals
 69    type: object
 70
 71    additionalProperties: true
 72
 73    required:
 74      - access-controllers
 75
 76required:
 77  - compatible
 78  - reg
 79  - "#address-cells"
 80  - "#size-cells"
 81  - "#access-controller-cells"
 82  - ranges
 83
 84additionalProperties: false
 85
 86examples:
 87  - |
 88    // In this example, the usart2 device refers to rifsc as its domain
 89    // controller.
 90    // Access rights are verified before creating devices.
 91
 92    #include <dt-bindings/interrupt-controller/arm-gic.h>
 93
 94    rifsc: bus@42080000 {
 95        compatible = "st,stm32mp25-rifsc", "simple-bus";
 96        reg = <0x42080000 0x1000>;
 97        #address-cells = <1>;
 98        #size-cells = <1>;
 99        #access-controller-cells = <1>;
100        ranges;
101
102        usart2: serial@400e0000 {
103              compatible = "st,stm32h7-uart";
104              reg = <0x400e0000 0x400>;
105              interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
106              clocks = <&ck_flexgen_08>;
107              access-controllers = <&rifsc 32>;
108        };
109    };