imx-sata.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/ata/imx-sata.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Freescale i.MX AHCI SATA Controller
  8
  9maintainers:
 10  - Shawn Guo <shawn.guo@linaro.org>
 11
 12description: |
 13  The Freescale i.MX SATA controller mostly conforms to the AHCI interface
 14  with some special extensions at integration level.
 15
 16properties:
 17  compatible:
 18    enum:
 19      - fsl,imx53-ahci
 20      - fsl,imx6q-ahci
 21      - fsl,imx6qp-ahci
 22      - fsl,imx8qm-ahci
 23
 24  reg:
 25    maxItems: 1
 26
 27  interrupts:
 28    maxItems: 1
 29
 30  clocks:
 31    minItems: 2
 32    items:
 33      - description: sata clock
 34      - description: sata reference clock
 35      - description: ahb clock
 36
 37  clock-names:
 38    minItems: 2
 39    items:
 40      - const: sata
 41      - const: sata_ref
 42      - const: ahb
 43
 44  fsl,transmit-level-mV:
 45    $ref: /schemas/types.yaml#/definitions/uint32
 46    description: transmit voltage level, in millivolts.
 47
 48  fsl,transmit-boost-mdB:
 49    $ref: /schemas/types.yaml#/definitions/uint32
 50    description: transmit boost level, in milli-decibels.
 51
 52  fsl,transmit-atten-16ths:
 53    $ref: /schemas/types.yaml#/definitions/uint32
 54    description: transmit attenuation, in 16ths.
 55
 56  fsl,receive-eq-mdB:
 57    $ref: /schemas/types.yaml#/definitions/uint32
 58    description: receive equalisation, in milli-decibels.
 59
 60  fsl,no-spread-spectrum:
 61    $ref: /schemas/types.yaml#/definitions/flag
 62    description: if present, disable spread-spectrum clocking on the SATA link.
 63
 64  phys:
 65    items:
 66      - description: phandle to SATA PHY.
 67          Since "REXT" pin is only present for first lane of i.MX8QM PHY, it's
 68          calibration result will be stored, passed through second lane, and
 69          shared with all three lanes PHY. The first two lanes PHY are used as
 70          calibration PHYs, although only the third lane PHY is used by SATA.
 71      - description: phandle to the first lane PHY of i.MX8QM.
 72      - description: phandle to the second lane PHY of i.MX8QM.
 73
 74  phy-names:
 75    items:
 76      - const: sata-phy
 77      - const: cali-phy0
 78      - const: cali-phy1
 79
 80  power-domains:
 81    maxItems: 1
 82
 83  target-supply:
 84    description: Power regulator for the SATA target device.
 85
 86required:
 87  - compatible
 88  - reg
 89  - interrupts
 90  - clocks
 91  - clock-names
 92
 93allOf:
 94  - if:
 95      properties:
 96        compatible:
 97          contains:
 98            enum:
 99              - fsl,imx53-ahci
100              - fsl,imx6q-ahci
101              - fsl,imx6qp-ahci
102    then:
103      properties:
104        clock-names:
105          minItems: 3
106
107  - if:
108      properties:
109        compatible:
110          contains:
111            enum:
112              - fsl,imx8qm-ahci
113    then:
114      properties:
115        clock-names:
116          minItems: 2
117
118additionalProperties: false
119
120examples:
121  - |
122    #include <dt-bindings/clock/imx6qdl-clock.h>
123    #include <dt-bindings/interrupt-controller/arm-gic.h>
124
125    sata@2200000 {
126        compatible = "fsl,imx6q-ahci";
127        reg = <0x02200000 0x4000>;
128        interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
129        clocks = <&clks IMX6QDL_CLK_SATA>,
130                 <&clks IMX6QDL_CLK_SATA_REF_100M>,
131                 <&clks IMX6QDL_CLK_AHB>;
132        clock-names = "sata", "sata_ref", "ahb";
133    };