nvidia,tegra186-pmc.yaml

  1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: NVIDIA Tegra Power Management Controller (PMC)
  8
  9maintainers:
 10  - Thierry Reding <thierry.reding@gmail.com>
 11  - Jon Hunter <jonathanh@nvidia.com>
 12
 13properties:
 14  compatible:
 15    enum:
 16      - nvidia,tegra186-pmc
 17      - nvidia,tegra194-pmc
 18      - nvidia,tegra234-pmc
 19      - nvidia,tegra264-pmc
 20
 21  reg:
 22    minItems: 4
 23    maxItems: 5
 24
 25  reg-names:
 26    minItems: 4
 27    items:
 28      - const: pmc
 29      - const: wake
 30      - const: aotag
 31      - enum: [ scratch, misc ]
 32      - const: misc
 33
 34  interrupt-controller: true
 35
 36  "#interrupt-cells":
 37    description: Specifies the number of cells needed to encode an
 38      interrupt source. The value must be 2.
 39    const: 2
 40
 41  nvidia,invert-interrupt:
 42    description: If present, inverts the PMU interrupt signal.
 43    $ref: /schemas/types.yaml#/definitions/flag
 44
 45allOf:
 46  - if:
 47      properties:
 48        compatible:
 49          contains:
 50            const: nvidia,tegra186-pmc
 51    then:
 52      properties:
 53        reg:
 54          maxItems: 4
 55        reg-names:
 56          maxItems: 4
 57          contains:
 58            const: scratch
 59
 60  - if:
 61      properties:
 62        compatible:
 63          contains:
 64            const: nvidia,tegra194-pmc
 65    then:
 66      properties:
 67        reg:
 68          minItems: 5
 69        reg-names:
 70          minItems: 5
 71
 72  - if:
 73      properties:
 74        compatible:
 75          contains:
 76            const: nvidia,tegra234-pmc
 77    then:
 78      properties:
 79        reg-names:
 80          contains:
 81            const: misc
 82
 83patternProperties:
 84  "^[a-z0-9]+-[a-z0-9]+$":
 85    if:
 86      type: object
 87    then:
 88      description: |
 89        These are pad configuration nodes. On Tegra SoCs a pad is a set of
 90        pins which are configured as a group. The pin grouping is a fixed
 91        attribute of the hardware. The PMC can be used to set pad power
 92        state and signaling voltage. A pad can be either in active or
 93        power down mode. The support for power state and signaling voltage
 94        configuration varies depending on the pad in question. 3.3 V and
 95        1.8 V signaling voltages are supported on pins where software
 96        controllable signaling voltage switching is available.
 97
 98        Pad configurations are described with pin configuration nodes
 99        which are placed under the pmc node and they are referred to by
100        the pinctrl client properties. For more information see
101
102          Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
103
104        The following pads are present on Tegra186:
105
106          csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
107          pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
108          hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
109          dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp,
110          sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv
111
112        The following pads are present on Tegra194:
113
114          csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
115          pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
116          pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12,
117          soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2,
118          hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
119          pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
120          spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
121          audio-hv, ao-hv
122
123      properties:
124        pins:
125          $ref: /schemas/types.yaml#/definitions/string
126          description: Must contain the name of the pad(s) to be
127            configured.
128
129        low-power-enable:
130          description: Configure the pad into power down mode.
131          $ref: /schemas/types.yaml#/definitions/flag
132
133        low-power-disable:
134          description: Configure the pad into active mode.
135          $ref: /schemas/types.yaml#/definitions/flag
136
137        power-source:
138          $ref: /schemas/types.yaml#/definitions/uint32
139          description: |
140            Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
141            TEGRA_IO_PAD_VOLTAGE_3V3 to select between signalling
142            voltages.
143
144            The values are defined in
145
146              include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
147
148            The power state can be configured on all of the above pads
149            except for ao-hv. Following pads have software configurable
150            signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
151            audio-hv, ao-hv.
152
153        phandle: true
154
155      required:
156        - pins
157
158      additionalProperties: false
159
160required:
161  - compatible
162  - reg
163  - reg-names
164
165additionalProperties: false
166
167dependencies:
168  interrupt-controller: ['#interrupt-cells']
169  "#interrupt-cells":
170    required:
171      - interrupt-controller
172
173examples:
174  - |
175    #include <dt-bindings/clock/tegra186-clock.h>
176    #include <dt-bindings/interrupt-controller/arm-gic.h>
177    #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
178    #include <dt-bindings/memory/tegra186-mc.h>
179    #include <dt-bindings/reset/tegra186-reset.h>
180
181    pmc@c3600000 {
182        compatible = "nvidia,tegra186-pmc";
183        reg = <0x0c360000 0x10000>,
184              <0x0c370000 0x10000>,
185              <0x0c380000 0x10000>,
186              <0x0c390000 0x10000>;
187        reg-names = "pmc", "wake", "aotag", "scratch";
188        nvidia,invert-interrupt;
189
190        sdmmc1_3v3: sdmmc1-3v3 {
191            pins = "sdmmc1-hv";
192            power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
193        };
194
195        sdmmc1_1v8: sdmmc1-1v8 {
196            pins = "sdmmc1-hv";
197            power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
198        };
199    };
200
201    sdmmc1: mmc@3400000 {
202        compatible = "nvidia,tegra186-sdhci";
203        reg = <0x03400000 0x10000>;
204        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
205        clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
206                 <&bpmp TEGRA186_CLK_SDMMC_LEGACY_TM>;
207        clock-names = "sdhci", "tmclk";
208        resets = <&bpmp TEGRA186_RESET_SDMMC1>;
209        reset-names = "sdhci";
210        interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
211                        <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
212        interconnect-names = "dma-mem", "write";
213        iommus = <&smmu TEGRA186_SID_SDMMC1>;
214        pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
215        pinctrl-0 = <&sdmmc1_3v3>;
216        pinctrl-1 = <&sdmmc1_1v8>;
217    };