allwinner,sun4i-a10-mbus.yaml

  1# SPDX-License-Identifier: GPL-2.0
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Allwinner Memory Bus (MBUS) controller
  8
  9maintainers:
 10  - Chen-Yu Tsai <wens@csie.org>
 11  - Maxime Ripard <mripard@kernel.org>
 12
 13description: |
 14  The MBUS controller drives the MBUS that other devices in the SoC
 15  will use to perform DMA. It also has a register interface that
 16  allows to monitor and control the bandwidth and priorities for
 17  masters on that bus.
 18
 19  Each device having to perform their DMA through the MBUS must have
 20  the interconnects and interconnect-names properties set to the MBUS
 21  controller and with "dma-mem" as the interconnect name.
 22
 23properties:
 24  "#interconnect-cells":
 25    const: 1
 26    description:
 27      The content of the cell is the MBUS ID.
 28
 29  compatible:
 30    enum:
 31      - allwinner,sun5i-a13-mbus
 32      - allwinner,sun8i-a33-mbus
 33      - allwinner,sun8i-a50-mbus
 34      - allwinner,sun8i-a83t-mbus
 35      - allwinner,sun8i-h3-mbus
 36      - allwinner,sun8i-r40-mbus
 37      - allwinner,sun8i-v3s-mbus
 38      - allwinner,sun8i-v536-mbus
 39      - allwinner,sun20i-d1-mbus
 40      - allwinner,sun50i-a64-mbus
 41      - allwinner,sun50i-a100-mbus
 42      - allwinner,sun50i-h5-mbus
 43      - allwinner,sun50i-h6-mbus
 44      - allwinner,sun50i-h616-mbus
 45      - allwinner,sun50i-r329-mbus
 46
 47  reg:
 48    minItems: 1
 49    items:
 50      - description: MBUS interconnect/bandwidth limit/PMU registers
 51      - description: DRAM controller/PHY registers
 52
 53  reg-names:
 54    minItems: 1
 55    items:
 56      - const: mbus
 57      - const: dram
 58
 59  clocks:
 60    minItems: 1
 61    items:
 62      - description: MBUS interconnect module clock
 63      - description: DRAM controller/PHY module clock
 64      - description: Register bus clock, shared by MBUS and DRAM
 65
 66  clock-names:
 67    minItems: 1
 68    items:
 69      - const: mbus
 70      - const: dram
 71      - const: bus
 72
 73  interrupts:
 74    maxItems: 1
 75    description:
 76      MBUS PMU activity interrupt.
 77
 78  dma-ranges:
 79    description:
 80      See section 2.3.9 of the DeviceTree Specification.
 81
 82  '#address-cells': true
 83
 84  '#size-cells': true
 85
 86required:
 87  - "#interconnect-cells"
 88  - compatible
 89  - reg
 90  - clocks
 91  - dma-ranges
 92
 93if:
 94  not:
 95    properties:
 96      compatible:
 97        contains:
 98          enum:
 99            - allwinner,sun5i-a13-mbus
100            - allwinner,sun8i-r40-mbus
101
102then:
103  properties:
104    reg:
105      minItems: 2
106
107    reg-names:
108      minItems: 2
109
110    clocks:
111      minItems: 3
112
113    clock-names:
114      minItems: 3
115
116  required:
117    - reg-names
118    - clock-names
119
120else:
121  properties:
122    reg:
123      maxItems: 1
124
125    reg-names:
126      maxItems: 1
127
128    clocks:
129      maxItems: 1
130
131    clock-names:
132      maxItems: 1
133
134additionalProperties: false
135
136examples:
137  - |
138    #include <dt-bindings/clock/sun50i-a64-ccu.h>
139    #include <dt-bindings/interrupt-controller/arm-gic.h>
140
141    dram-controller@1c01000 {
142        compatible = "allwinner,sun5i-a13-mbus";
143        reg = <0x01c01000 0x1000>;
144        clocks = <&ccu CLK_MBUS>;
145        #address-cells = <1>;
146        #size-cells = <1>;
147        dma-ranges = <0x00000000 0x40000000 0x20000000>;
148        #interconnect-cells = <1>;
149    };
150
151  - |
152    dram-controller@1c62000 {
153        compatible = "allwinner,sun50i-a64-mbus";
154        reg = <0x01c62000 0x1000>,
155              <0x01c63000 0x1000>;
156        reg-names = "mbus", "dram";
157        clocks = <&ccu CLK_MBUS>,
158                 <&ccu CLK_DRAM>,
159                 <&ccu CLK_BUS_DRAM>;
160        clock-names = "mbus", "dram", "bus";
161        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
162        #address-cells = <1>;
163        #size-cells = <1>;
164        dma-ranges = <0x00000000 0x40000000 0xc0000000>;
165        #interconnect-cells = <1>;
166    };
167
168...