pmu.yaml

  1# SPDX-License-Identifier: GPL-2.0
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/arm/pmu.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: ARM Performance Monitor Units
  8
  9maintainers:
 10  - Mark Rutland <mark.rutland@arm.com>
 11  - Will Deacon <will.deacon@arm.com>
 12
 13description: |+
 14  ARM cores often have a PMU for counting cpu and cache events like cache misses
 15  and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
 16  representation in the device tree should be done as under:-
 17
 18properties:
 19  compatible:
 20    items:
 21      - enum:
 22          - apm,potenza-pmu
 23          - apple,avalanche-pmu
 24          - apple,blizzard-pmu
 25          - apple,firestorm-pmu
 26          - apple,icestorm-pmu
 27          - arm,armv8-pmuv3 # Only for s/w models
 28          - arm,arm1136-pmu
 29          - arm,arm1176-pmu
 30          - arm,arm11mpcore-pmu
 31          - arm,c1-nano-pmu
 32          - arm,c1-premium-pmu
 33          - arm,c1-pro-pmu
 34          - arm,c1-ultra-pmu
 35          - arm,cortex-a5-pmu
 36          - arm,cortex-a7-pmu
 37          - arm,cortex-a8-pmu
 38          - arm,cortex-a9-pmu
 39          - arm,cortex-a12-pmu
 40          - arm,cortex-a15-pmu
 41          - arm,cortex-a17-pmu
 42          - arm,cortex-a32-pmu
 43          - arm,cortex-a34-pmu
 44          - arm,cortex-a35-pmu
 45          - arm,cortex-a53-pmu
 46          - arm,cortex-a55-pmu
 47          - arm,cortex-a57-pmu
 48          - arm,cortex-a65-pmu
 49          - arm,cortex-a72-pmu
 50          - arm,cortex-a73-pmu
 51          - arm,cortex-a75-pmu
 52          - arm,cortex-a76-pmu
 53          - arm,cortex-a77-pmu
 54          - arm,cortex-a78-pmu
 55          - arm,cortex-a320-pmu
 56          - arm,cortex-a510-pmu
 57          - arm,cortex-a520-pmu
 58          - arm,cortex-a520ae-pmu
 59          - arm,cortex-a710-pmu
 60          - arm,cortex-a715-pmu
 61          - arm,cortex-a720-pmu
 62          - arm,cortex-a720ae-pmu
 63          - arm,cortex-a725-pmu
 64          - arm,cortex-x1-pmu
 65          - arm,cortex-x2-pmu
 66          - arm,cortex-x3-pmu
 67          - arm,cortex-x4-pmu
 68          - arm,cortex-x925-pmu
 69          - arm,neoverse-e1-pmu
 70          - arm,neoverse-n1-pmu
 71          - arm,neoverse-n2-pmu
 72          - arm,neoverse-n3-pmu
 73          - arm,neoverse-v1-pmu
 74          - arm,neoverse-v2-pmu
 75          - arm,neoverse-v3-pmu
 76          - arm,neoverse-v3ae-pmu
 77          - arm,rainier-pmu
 78          - brcm,vulcan-pmu
 79          - cavium,thunder-pmu
 80          - nvidia,denver-pmu
 81          - nvidia,carmel-pmu
 82          - qcom,krait-pmu
 83          - qcom,scorpion-pmu
 84          - qcom,scorpion-mp-pmu
 85          - samsung,mongoose-pmu
 86
 87  interrupts:
 88    # Don't know how many CPUs, so no constraints to specify
 89    description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
 90
 91  interrupt-affinity:
 92    $ref: /schemas/types.yaml#/definitions/phandle-array
 93    items:
 94      maxItems: 1
 95    description:
 96      When using SPIs, specifies a list of phandles to CPU
 97      nodes corresponding directly to the affinity of
 98      the SPIs listed in the interrupts property.
 99
100      When using a PPI, specifies a list of phandles to CPU
101      nodes corresponding to the set of CPUs which have
102      a PMU of this type signalling the PPI listed in the
103      interrupts property, unless this is already specified
104      by the PPI interrupt specifier itself (in which case
105      the interrupt-affinity property shouldn't be present).
106
107      This property should be present when there is more than
108      a single SPI.
109
110  qcom,no-pc-write:
111    type: boolean
112    description:
113      Indicates that this PMU doesn't support the 0xc and 0xd events.
114
115  secure-reg-access:
116    type: boolean
117    description:
118      Indicates that the ARMv7 Secure Debug Enable Register
119      (SDER) is accessible. This will cause the driver to do
120      any setup required that is only possible in ARMv7 secure
121      state. If not present the ARMv7 SDER will not be touched,
122      which means the PMU may fail to operate unless external
123      code (bootloader or security monitor) has performed the
124      appropriate initialisation. Note that this property is
125      not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
126      in Non-secure state.
127
128required:
129  - compatible
130
131additionalProperties: false
132
133...