mediatek,audsys.yaml

  1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/arm/mediatek/mediatek,audsys.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: MediaTek AUDSYS controller
  8
  9maintainers:
 10  - Eugen Hristev <eugen.hristev@collabora.com>
 11
 12description:
 13  The MediaTek AUDSYS controller provides various clocks to the system.
 14
 15properties:
 16  compatible:
 17    oneOf:
 18      - items:
 19          - enum:
 20              - mediatek,mt2701-audsys
 21              - mediatek,mt6765-audsys
 22              - mediatek,mt6779-audsys
 23              - mediatek,mt7622-audsys
 24              - mediatek,mt8167-audsys
 25              - mediatek,mt8173-audsys
 26              - mediatek,mt8183-audiosys
 27              - mediatek,mt8183-audsys
 28              - mediatek,mt8186-audsys
 29              - mediatek,mt8192-audsys
 30              - mediatek,mt8516-audsys
 31          - const: syscon
 32      - items:
 33          # Special case for mt7623 for backward compatibility
 34          - const: mediatek,mt7623-audsys
 35          - const: mediatek,mt2701-audsys
 36          - const: syscon
 37
 38  reg:
 39    maxItems: 1
 40
 41  '#clock-cells':
 42    const: 1
 43
 44  audio-controller:
 45    type: object
 46
 47required:
 48  - compatible
 49  - '#clock-cells'
 50
 51if:
 52  properties:
 53    compatible:
 54      contains:
 55        const: mediatek,mt8183-audiosys
 56then:
 57  properties:
 58    audio-controller:
 59      $ref: /schemas/sound/mediatek,mt8183-audio.yaml#
 60else:
 61  properties:
 62    audio-controller:
 63      $ref: /schemas/sound/mediatek,mt2701-audio.yaml#
 64
 65additionalProperties: false
 66
 67examples:
 68  - |
 69    #include <dt-bindings/interrupt-controller/arm-gic.h>
 70    #include <dt-bindings/interrupt-controller/irq.h>
 71    #include <dt-bindings/power/mt2701-power.h>
 72    #include <dt-bindings/clock/mt2701-clk.h>
 73    soc {
 74        #address-cells = <2>;
 75        #size-cells = <2>;
 76        audsys: clock-controller@11220000 {
 77            compatible = "mediatek,mt7622-audsys", "syscon";
 78            reg = <0 0x11220000 0 0x2000>;
 79            #clock-cells = <1>;
 80
 81            afe: audio-controller {
 82                compatible = "mediatek,mt2701-audio";
 83                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
 84                             <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 85                interrupt-names = "afe", "asys";
 86                power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
 87
 88                clocks = <&infracfg CLK_INFRA_AUDIO>,
 89                         <&topckgen CLK_TOP_AUD_MUX1_SEL>,
 90                         <&topckgen CLK_TOP_AUD_MUX2_SEL>,
 91                         <&topckgen CLK_TOP_AUD_48K_TIMING>,
 92                         <&topckgen CLK_TOP_AUD_44K_TIMING>,
 93                         <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
 94                         <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
 95                         <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
 96                         <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
 97                         <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
 98                         <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
 99                         <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
100                         <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
101                         <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
102                         <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
103                         <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
104                         <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
105                         <&audsys CLK_AUD_I2SO1>,
106                         <&audsys CLK_AUD_I2SO2>,
107                         <&audsys CLK_AUD_I2SO3>,
108                         <&audsys CLK_AUD_I2SO4>,
109                         <&audsys CLK_AUD_I2SIN1>,
110                         <&audsys CLK_AUD_I2SIN2>,
111                         <&audsys CLK_AUD_I2SIN3>,
112                         <&audsys CLK_AUD_I2SIN4>,
113                         <&audsys CLK_AUD_ASRCO1>,
114                         <&audsys CLK_AUD_ASRCO2>,
115                         <&audsys CLK_AUD_ASRCO3>,
116                         <&audsys CLK_AUD_ASRCO4>,
117                         <&audsys CLK_AUD_AFE>,
118                         <&audsys CLK_AUD_AFE_CONN>,
119                         <&audsys CLK_AUD_A1SYS>,
120                         <&audsys CLK_AUD_A2SYS>,
121                         <&audsys CLK_AUD_AFE_MRGIF>;
122
123                clock-names = "infra_sys_audio_clk",
124                              "top_audio_mux1_sel",
125                              "top_audio_mux2_sel",
126                              "top_audio_a1sys_hp",
127                              "top_audio_a2sys_hp",
128                              "i2s0_src_sel",
129                              "i2s1_src_sel",
130                              "i2s2_src_sel",
131                              "i2s3_src_sel",
132                              "i2s0_src_div",
133                              "i2s1_src_div",
134                              "i2s2_src_div",
135                              "i2s3_src_div",
136                              "i2s0_mclk_en",
137                              "i2s1_mclk_en",
138                              "i2s2_mclk_en",
139                              "i2s3_mclk_en",
140                              "i2so0_hop_ck",
141                              "i2so1_hop_ck",
142                              "i2so2_hop_ck",
143                              "i2so3_hop_ck",
144                              "i2si0_hop_ck",
145                              "i2si1_hop_ck",
146                              "i2si2_hop_ck",
147                              "i2si3_hop_ck",
148                              "asrc0_out_ck",
149                              "asrc1_out_ck",
150                              "asrc2_out_ck",
151                              "asrc3_out_ck",
152                              "audio_afe_pd",
153                              "audio_afe_conn_pd",
154                              "audio_a1sys_pd",
155                              "audio_a2sys_pd",
156                              "audio_mrgif_pd";
157
158                assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
159                                  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
160                                  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
161                                  <&topckgen CLK_TOP_AUD_MUX2_DIV>;
162                assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
163                                         <&topckgen CLK_TOP_AUD2PLL_90M>;
164                assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
165            };
166        };
167    };