cci-control-port.yaml

 1# SPDX-License-Identifier: GPL-2.0
 2%YAML 1.2
 3---
 4$id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
 5$schema: http://devicetree.org/meta-schemas/core.yaml#
 6
 7title: CCI Interconnect Bus Masters
 8
 9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |
13  Masters in the device tree connected to a CCI port (inclusive of CPUs
14  and their cpu nodes).
15
16select: true
17
18properties:
19  cci-control-port:
20    $ref: /schemas/types.yaml#/definitions/phandle
21
22additionalProperties: true
23
24examples:
25  - |
26    cpus {
27        #address-cells = <1>;
28        #size-cells = <0>;
29
30        cpu@0 {
31            compatible = "arm,cortex-a15";
32            device_type = "cpu";
33            cci-control-port = <&cci_control1>;
34            reg = <0>;
35        };
36    };
37
38...