brcm,brcmstb.txt

  1ARM Broadcom STB platforms Device Tree Bindings
  2-----------------------------------------------
  3Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
  4SoC shall have the following DT organization:
  5
  6Required root node properties:
  7    - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
  8
  9example:
 10/ {
 11    #address-cells = <2>;
 12    #size-cells = <2>;
 13    model = "Broadcom STB (bcm7445)";
 14    compatible = "brcm,bcm7445", "brcm,brcmstb";
 15
 16Further, syscon nodes that map platform-specific registers used for general
 17system control is required:
 18
 19    - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
 20    - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
 21		  "brcm,brcmstb-cpu-biu-ctrl",
 22		  "syscon"
 23    - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
 24
 25cpu-biu-ctrl node
 26-------------------
 27SoCs with Broadcom Brahma15 ARM-based and Brahma53 ARM64-based CPUs have a
 28specific Bus Interface Unit (BIU) block which controls and interfaces the CPU
 29complex to the different Memory Controller Ports (MCP), one per memory
 30controller (MEMC). This BIU block offers a feature called Write Pairing which
 31consists in collapsing two adjacent cache lines into a single (bursted) write
 32transaction towards the memory controller (MEMC) to maximize write bandwidth.
 33
 34Required properties:
 35
 36    - compatible: must be "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon"
 37
 38Optional properties:
 39
 40    - brcm,write-pairing:
 41	Boolean property, which when present indicates that the chip
 42	supports write-pairing.
 43
 44example:
 45    rdb {
 46        #address-cells = <1>;
 47        #size-cells = <1>;
 48        compatible = "simple-bus";
 49        ranges = <0 0x00 0xf0000000 0x1000000>;
 50
 51        sun_top_ctrl: syscon@404000 {
 52            compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
 53            reg = <0x404000 0x51c>;
 54        };
 55
 56        hif_cpubiuctrl: syscon@3e2400 {
 57            compatible = "brcm,bcm7445-cpu-biu-ctrl", "brcm,brcmstb-cpu-biu-ctrl", "syscon";
 58            reg = <0x3e2400 0x5b4>;
 59            brcm,write-pairing;
 60        };
 61
 62        hif_continuation: syscon@452000 {
 63            compatible = "brcm,bcm7445-hif-continuation", "syscon";
 64            reg = <0x452000 0x100>;
 65        };
 66    };
 67
 68Nodes that allow for support of SMP initialization and reboot are required:
 69
 70smpboot
 71-------
 72Required properties:
 73
 74    - compatible
 75        The string "brcm,brcmstb-smpboot".
 76
 77    - syscon-cpu
 78        A phandle / integer array property which lets the BSP know the location
 79        of certain CPU power-on registers.
 80
 81        The layout of the property is as follows:
 82            o a phandle to the "hif_cpubiuctrl" syscon node
 83            o offset to the base CPU power zone register
 84            o offset to the base CPU reset register
 85
 86    - syscon-cont
 87        A phandle pointing to the syscon node which describes the CPU boot
 88        continuation registers.
 89            o a phandle to the "hif_continuation" syscon node
 90
 91example:
 92    smpboot {
 93        compatible = "brcm,brcmstb-smpboot";
 94        syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
 95        syscon-cont = <&hif_continuation>;
 96    };
 97
 98reboot
 99-------
100Required properties
101
102    - compatible
103        The string property "brcm,brcmstb-reboot" for 40nm/28nm chips with
104        the new SYS_CTRL interface, or "brcm,bcm7038-reboot" for 65nm
105        chips with the old SUN_TOP_CTRL interface.
106
107    - syscon
108        A phandle / integer array that points to the syscon node which describes
109        the general system reset registers.
110            o a phandle to "sun_top_ctrl"
111            o offset to the "reset source enable" register
112            o offset to the "software master reset" register
113
114example:
115    reboot {
116        compatible = "brcm,brcmstb-reboot";
117        syscon = <&sun_top_ctrl 0x304 0x308>;
118    };
119
120
121
122Power management
123----------------
124
125For power management (particularly, S2/S3/S5 system suspend), the following SoC
126components are needed:
127
128= Always-On control block (AON CTRL)
129
130This hardware provides control registers for the "always-on" (even in low-power
131modes) hardware, such as the Power Management State Machine (PMSM).
132
133Required properties:
134- compatible     : should contain "brcm,brcmstb-aon-ctrl"
135- reg            : the register start and length for the AON CTRL block
136
137Example:
138
139aon-ctrl@410000 {
140	compatible = "brcm,brcmstb-aon-ctrl";
141	reg = <0x410000 0x400>;
142};
143
144= Memory controllers
145
146A Broadcom STB SoC typically has a number of independent memory controllers,
147each of which may have several associated hardware blocks, which are versioned
148independently (control registers, DDR PHYs, etc.). One might consider
149describing these controllers as a parent "memory controllers" block, which
150contains N sub-nodes (one for each controller in the system), each of which is
151associated with a number of hardware register resources (e.g., its PHY). See
152the example device tree snippet below.
153
154== MEMC (MEMory Controller)
155
156Represents a single memory controller instance.
157
158Required properties:
159- compatible     : should contain "brcm,brcmstb-memc" and "simple-bus"
160
161Should contain subnodes for any of the following relevant hardware resources:
162
163== DDR PHY control
164
165Control registers for this memory controller's DDR PHY.
166
167Required properties:
168- compatible     : should contain one of these
169	"brcm,brcmstb-ddr-phy-v71.1"
170	"brcm,brcmstb-ddr-phy-v72.0"
171	"brcm,brcmstb-ddr-phy-v225.1"
172	"brcm,brcmstb-ddr-phy-v240.1"
173	"brcm,brcmstb-ddr-phy-v240.2"
174
175- reg            : the DDR PHY register range
176
177== DDR SHIMPHY
178
179Control registers for this memory controller's DDR SHIMPHY.
180
181Required properties:
182- compatible     : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
183- reg            : the DDR SHIMPHY register range
184
185== MEMC DDR control
186
187Sequencer DRAM parameters and control registers. Used for Self-Refresh
188Power-Down (SRPD), among other things.
189
190See Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml for a
191full list of supported compatible strings and properties.
192
193Example:
194
195memory_controllers {
196	ranges;
197	compatible = "simple-bus";
198
199	memc@0 {
200		compatible = "brcm,brcmstb-memc", "simple-bus";
201		ranges;
202
203		ddr-phy@f1106000 {
204			compatible = "brcm,brcmstb-ddr-phy-v240.1";
205			reg = <0xf1106000 0x21c>;
206		};
207
208		shimphy@f1108000 {
209			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
210			reg = <0xf1108000 0xe4>;
211		};
212
213		memc-ddr@f1102000 {
214			reg = <0xf1102000 0x800>;
215			compatible = "brcm,brcmstb-memc-ddr";
216		};
217	};
218
219	memc@1 {
220		compatible = "brcm,brcmstb-memc", "simple-bus";
221		ranges;
222
223		ddr-phy@f1186000 {
224			compatible = "brcm,brcmstb-ddr-phy-v240.1";
225			reg = <0xf1186000 0x21c>;
226		};
227
228		shimphy@f1188000 {
229			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
230			reg = <0xf1188000 0xe4>;
231		};
232
233		memc-ddr@f1182000 {
234			reg = <0xf1182000 0x800>;
235			compatible = "brcm,brcmstb-memc-ddr";
236		};
237	};
238
239	memc@2 {
240		compatible = "brcm,brcmstb-memc", "simple-bus";
241		ranges;
242
243		ddr-phy@f1206000 {
244			compatible = "brcm,brcmstb-ddr-phy-v240.1";
245			reg = <0xf1206000 0x21c>;
246		};
247
248		shimphy@f1208000 {
249			compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
250			reg = <0xf1208000 0xe4>;
251		};
252
253		memc-ddr@f1202000 {
254			reg = <0xf1202000 0x800>;
255			compatible = "brcm,brcmstb-memc-ddr";
256		};
257	};
258};