arm,coresight-tmc.yaml

  1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/arm/arm,coresight-tmc.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Arm CoreSight Trace Memory Controller
  8
  9maintainers:
 10  - Mathieu Poirier <mathieu.poirier@linaro.org>
 11  - Mike Leach <mike.leach@linaro.org>
 12  - Leo Yan <leo.yan@linaro.org>
 13  - Suzuki K Poulose <suzuki.poulose@arm.com>
 14
 15description: |
 16  CoreSight components are compliant with the ARM CoreSight architecture
 17  specification and can be connected in various topologies to suit a particular
 18  SoCs tracing needs. These trace components can generally be classified as
 19  sinks, links and sources. Trace data produced by one or more sources flows
 20  through the intermediate links connecting the source to the currently selected
 21  sink.
 22
 23  Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace
 24  FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
 25  mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
 26
 27# Need a custom select here or 'arm,primecell' will match on lots of nodes
 28select:
 29  properties:
 30    compatible:
 31      contains:
 32        const: arm,coresight-tmc
 33  required:
 34    - compatible
 35
 36allOf:
 37  - $ref: /schemas/arm/primecell.yaml#
 38
 39properties:
 40  compatible:
 41    items:
 42      - const: arm,coresight-tmc
 43      - const: arm,primecell
 44
 45  reg:
 46    maxItems: 1
 47
 48  clocks:
 49    minItems: 1
 50    maxItems: 2
 51
 52  clock-names:
 53    minItems: 1
 54    items:
 55      - const: apb_pclk
 56      - const: atclk
 57
 58  label:
 59    description:
 60      Description of a coresight device.
 61
 62  iommus:
 63    maxItems: 1
 64
 65  power-domains:
 66    maxItems: 1
 67
 68  arm,buffer-size:
 69    $ref: /schemas/types.yaml#/definitions/uint32
 70    deprecated: true
 71    description:
 72      Size of contiguous buffer space for TMC ETR (embedded trace router). The
 73      buffer size can be configured dynamically via buffer_size property in
 74      sysfs instead.
 75
 76  arm,scatter-gather:
 77    type: boolean
 78    description:
 79      Indicates that the TMC-ETR can safely use the SG mode on this system.
 80
 81  arm,max-burst-size:
 82    description:
 83      The maximum burst size initiated by TMC on the AXI master interface. The
 84      burst size can be in the range [0..15], the setting supports one data
 85      transfer per burst up to a maximum of 16 data transfers per burst.
 86    $ref: /schemas/types.yaml#/definitions/uint32
 87    maximum: 15
 88
 89  in-ports:
 90    $ref: /schemas/graph.yaml#/properties/ports
 91    additionalProperties: false
 92
 93    properties:
 94      port:
 95        description: Input connection from the CoreSight Trace bus.
 96        $ref: /schemas/graph.yaml#/properties/port
 97
 98  out-ports:
 99    $ref: /schemas/graph.yaml#/properties/ports
100    additionalProperties: false
101
102    properties:
103      port:
104        description: AXI or ATB Master output connection. Used for ETR
105          and ETF configurations.
106        $ref: /schemas/graph.yaml#/properties/port
107
108  memory-region:
109    items:
110      - description: Reserved trace buffer memory for ETR and ETF sinks.
111          For ETR, this reserved memory region is used for trace data capture.
112          Same region is used for trace data retention as well after a panic
113          or watchdog reset.
114          This reserved memory region is used as trace buffer or used for trace
115          data retention only if specifically selected by the user in sysfs
116          interface.
117          The default memory usage models for ETR in sysfs/perf modes are
118          otherwise unaltered.
119
120          For ETF, this reserved memory region is used by default for
121          retention of trace data synced from internal SRAM after a panic
122          or watchdog reset.
123      - description: Reserved meta data memory. Used for ETR and ETF sinks
124          for storing metadata.
125
126  memory-region-names:
127    items:
128      - const: tracedata
129      - const: metadata
130
131required:
132  - compatible
133  - reg
134  - clocks
135  - clock-names
136  - in-ports
137
138unevaluatedProperties: false
139
140examples:
141  - |
142    etr@20070000 {
143        compatible = "arm,coresight-tmc", "arm,primecell";
144        reg = <0x20070000 0x1000>;
145        memory-region = <&etr_trace_mem_reserved>,
146                       <&etr_mdata_mem_reserved>;
147        memory-region-names = "tracedata", "metadata";
148
149        clocks = <&oscclk6a>;
150        clock-names = "apb_pclk";
151        in-ports {
152            port {
153                etr_in_port: endpoint {
154                    remote-endpoint = <&replicator2_out_port0>;
155                };
156            };
157        };
158
159        out-ports {
160            port {
161                etr_out_port: endpoint {
162                    remote-endpoint = <&catu_in_port>;
163                };
164            };
165        };
166    };
167...