arm,cci-400.yaml

  1# SPDX-License-Identifier: GPL-2.0
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: ARM CCI Cache Coherent Interconnect
  8
  9maintainers:
 10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
 11
 12description: >
 13  ARM multi-cluster systems maintain intra-cluster coherency through a cache
 14  coherent interconnect (CCI) that is capable of monitoring bus transactions
 15  and manage coherency, TLB invalidations and memory barriers.
 16
 17  It allows snooping and distributed virtual memory message broadcast across
 18  clusters, through memory mapped interface, with a global control register
 19  space and multiple sets of interface control registers, one per slave
 20  interface.
 21
 22properties:
 23  $nodename:
 24    pattern: "^cci(@[0-9a-f]+)?$"
 25
 26  compatible:
 27    enum:
 28      - arm,cci-400
 29      - arm,cci-500
 30      - arm,cci-550
 31
 32  reg:
 33    maxItems: 1
 34    description: >
 35      Specifies base physical address of CCI control registers common to all
 36      interfaces.
 37
 38  "#address-cells": true
 39  "#size-cells": true
 40  ranges: true
 41
 42patternProperties:
 43  "^slave-if@[0-9a-f]+$":
 44    type: object
 45
 46    properties:
 47      compatible:
 48        const: arm,cci-400-ctrl-if
 49
 50      interface-type:
 51        enum:
 52          - ace
 53          - ace-lite
 54
 55      reg:
 56        maxItems: 1
 57
 58    required:
 59      - compatible
 60      - interface-type
 61      - reg
 62
 63    additionalProperties: false
 64
 65  "^pmu@[0-9a-f]+$":
 66    type: object
 67
 68    properties:
 69      compatible:
 70        oneOf:
 71          - const: arm,cci-400-pmu,r0
 72          - const: arm,cci-400-pmu,r1
 73          - const: arm,cci-400-pmu
 74            deprecated: true
 75            description: >
 76              Permitted only where OS has secure access to CCI registers
 77          - const: arm,cci-500-pmu,r0
 78          - const: arm,cci-550-pmu,r0
 79
 80      interrupts:
 81        minItems: 1
 82        maxItems: 8
 83        description: >
 84          List of counter overflow interrupts, one per counter. The interrupts
 85          must be specified starting with the cycle counter overflow interrupt,
 86          followed by counter0 overflow interrupt, counter1 overflow
 87          interrupt,...  ,counterN overflow interrupt.
 88
 89          The CCI PMU has an interrupt signal for each counter. The number of
 90          interrupts must be equal to the number of counters.
 91
 92      reg:
 93        maxItems: 1
 94
 95    required:
 96      - compatible
 97      - interrupts
 98      - reg
 99
100    additionalProperties: false
101
102required:
103  - "#address-cells"
104  - "#size-cells"
105  - compatible
106  - ranges
107  - reg
108
109additionalProperties: false
110
111examples:
112  - |
113      / {
114          #address-cells = <2>;
115          #size-cells = <2>;
116
117          compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
118          model = "V2P-CA15_CA7";
119          arm,hbi = <0x249>;
120          interrupt-parent = <&gic>;
121
122          gic: interrupt-controller {
123              interrupt-controller;
124              #interrupt-cells = <3>;
125          };
126
127          /*
128           * This CCI node corresponds to a CCI component whose control
129           * registers sits at address 0x000000002c090000.
130           *
131           * CCI slave interface @0x000000002c091000 is connected to dma
132           * controller dma0.
133           *
134           * CCI slave interface @0x000000002c094000 is connected to CPUs
135           * {CPU0, CPU1};
136           *
137           * CCI slave interface @0x000000002c095000 is connected to CPUs
138           * {CPU2, CPU3};
139           */
140
141          cpus {
142              #size-cells = <0>;
143              #address-cells = <1>;
144
145              CPU0: cpu@0 {
146                  device_type = "cpu";
147                  compatible = "arm,cortex-a15";
148                  cci-control-port = <&cci_control1>;
149                  reg = <0x0>;
150              };
151
152              CPU1: cpu@1 {
153                  device_type = "cpu";
154                  compatible = "arm,cortex-a15";
155                  cci-control-port = <&cci_control1>;
156                  reg = <0x1>;
157              };
158
159              CPU2: cpu@100 {
160                  device_type = "cpu";
161                  compatible = "arm,cortex-a7";
162                  cci-control-port = <&cci_control2>;
163                  reg = <0x100>;
164              };
165
166              CPU3: cpu@101 {
167                  device_type = "cpu";
168                  compatible = "arm,cortex-a7";
169                  cci-control-port = <&cci_control2>;
170                  reg = <0x101>;
171              };
172          };
173
174          cci@2c090000 {
175              compatible = "arm,cci-400";
176              #address-cells = <1>;
177              #size-cells = <1>;
178              reg = <0x0 0x2c090000 0 0x1000>;
179              ranges = <0x0 0x0 0x2c090000 0x10000>;
180
181              cci_control0: slave-if@1000 {
182                  compatible = "arm,cci-400-ctrl-if";
183                  interface-type = "ace-lite";
184                  reg = <0x1000 0x1000>;
185              };
186
187              cci_control1: slave-if@4000 {
188                  compatible = "arm,cci-400-ctrl-if";
189                  interface-type = "ace";
190                  reg = <0x4000 0x1000>;
191              };
192
193              cci_control2: slave-if@5000 {
194                  compatible = "arm,cci-400-ctrl-if";
195                  interface-type = "ace";
196                  reg = <0x5000 0x1000>;
197              };
198
199              pmu@9000 {
200                  compatible = "arm,cci-400-pmu";
201                  reg = <0x9000 0x5000>;
202                  interrupts = <0 101 4>,
203                    <0 102 4>,
204                    <0 103 4>,
205                    <0 104 4>,
206                    <0 105 4>;
207              };
208          };
209      };
210
211...