socfpga-clk-manager.yaml

  1# SPDX-License-Identifier: GPL-2.0
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Altera SOCFPGA Clock Manager
  8
  9maintainers:
 10  - Dinh Nguyen <dinguyen@kernel.org>
 11
 12description:
 13  This binding describes the Altera SOCFGPA Clock Manager and its associated
 14  tree of clocks, pll's, and clock gates for the Cyclone5, Arria5 and Arria10
 15  chip families.
 16
 17properties:
 18  compatible:
 19    items:
 20      - const: altr,clk-mgr
 21
 22  reg:
 23    maxItems: 1
 24
 25  clocks:
 26    type: object
 27    additionalProperties: false
 28
 29    properties:
 30      '#address-cells':
 31        const: 1
 32
 33      '#size-cells':
 34        const: 0
 35
 36    patternProperties:
 37      '^osc[0-9]$':
 38        type: object
 39
 40      '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$':
 41        type: object
 42        $ref: '#/$defs/clock-props'
 43        unevaluatedProperties: false
 44
 45        properties:
 46          compatible:
 47            enum:
 48              - altr,socfpga-pll-clock
 49              - altr,socfpga-perip-clk
 50              - altr,socfpga-gate-clk
 51              - altr,socfpga-a10-pll-clock
 52              - altr,socfpga-a10-perip-clk
 53              - altr,socfpga-a10-gate-clk
 54              - fixed-clock
 55
 56          clocks:
 57            description: one or more phandles to input clock
 58            minItems: 1
 59            maxItems: 5
 60
 61          '#address-cells':
 62            const: 1
 63
 64          '#size-cells':
 65            const: 0
 66
 67        patternProperties:
 68          '^[a-z0-9,_]+(clk|pll)(@[a-f0-9]+)?$':
 69            type: object
 70            $ref: '#/$defs/clock-props'
 71            unevaluatedProperties: false
 72
 73            properties:
 74              compatible:
 75                enum:
 76                  - altr,socfpga-perip-clk
 77                  - altr,socfpga-gate-clk
 78                  - altr,socfpga-a10-perip-clk
 79                  - altr,socfpga-a10-gate-clk
 80
 81              clocks:
 82                description: one or more phandles to input clock
 83                minItems: 1
 84                maxItems: 4
 85
 86            required:
 87              - compatible
 88              - clocks
 89              - '#clock-cells'
 90
 91        required:
 92          - compatible
 93          - '#clock-cells'
 94
 95required:
 96  - compatible
 97  - reg
 98
 99additionalProperties: false
100
101$defs:
102  clock-props:
103    properties:
104      reg:
105        maxItems: 1
106
107      '#clock-cells':
108        const: 0
109
110      clk-gate:
111        $ref: /schemas/types.yaml#/definitions/uint32-array
112        items:
113          - description: gating register offset
114          - description: bit index
115
116      div-reg:
117        $ref: /schemas/types.yaml#/definitions/uint32-array
118        items:
119          - description: divider register offset
120          - description: bit shift
121          - description: bit width
122
123      fixed-divider:
124        $ref: /schemas/types.yaml#/definitions/uint32
125
126examples:
127  - |
128    clkmgr@ffd04000 {
129      compatible = "altr,clk-mgr";
130      reg = <0xffd04000 0x1000>;
131    };
132
133...