sysfs-bus-event_source-devices-hisi_ptt

  1What:		/sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune
  2Date:		October 2022
  3KernelVersion:	6.1
  4Contact:	Yicong Yang <yangyicong@hisilicon.com>
  5Description:	This directory contains files for tuning the PCIe link
  6		parameters(events). Each file is named after the event
  7		of the PCIe link.
  8
  9		See Documentation/trace/hisi-ptt.rst for more information.
 10
 11What:		/sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_cpl
 12Date:		October 2022
 13KernelVersion:	6.1
 14Contact:	Yicong Yang <yangyicong@hisilicon.com>
 15Description:	(RW) Controls the weight of Tx completion TLPs, which influence
 16		the proportion of outbound completion TLPs on the PCIe link.
 17		The available tune data is [0, 1, 2]. Writing a negative value
 18		will return an error, and out of range values will be converted
 19		to 2. The value indicates a probable level of the event.
 20
 21What:		/sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_np
 22Date:		October 2022
 23KernelVersion:	6.1
 24Contact:	Yicong Yang <yangyicong@hisilicon.com>
 25Description:	(RW) Controls the weight of Tx non-posted TLPs, which influence
 26		the proportion of outbound non-posted TLPs on the PCIe link.
 27		The available tune data is [0, 1, 2]. Writing a negative value
 28		will return an error, and out of range values will be converted
 29		to 2. The value indicates a probable level of the event.
 30
 31What:		/sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_p
 32Date:		October 2022
 33KernelVersion:	6.1
 34Contact:	Yicong Yang <yangyicong@hisilicon.com>
 35Description:	(RW) Controls the weight of Tx posted TLPs, which influence the
 36		proportion of outbound posted TLPs on the PCIe link.
 37		The available tune data is [0, 1, 2]. Writing a negative value
 38		will return an error, and out of range values will be converted
 39		to 2. The value indicates a probable level of the event.
 40
 41What:		/sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune/rx_alloc_buf_level
 42Date:		October 2022
 43KernelVersion:	6.1
 44Contact:	Yicong Yang <yangyicong@hisilicon.com>
 45Description:	(RW) Control the allocated buffer watermark for inbound packets.
 46		The packets will be stored in the buffer first and then transmitted
 47		either when the watermark reached or when timed out.
 48		The available tune data is [0, 1, 2]. Writing a negative value
 49		will return an error, and out of range values will be converted
 50		to 2. The value indicates a probable level of the event.
 51
 52What:		/sys/bus/event_source/devices/hisi_ptt<sicl_id>_<core_id>/tune/tx_alloc_buf_level
 53Date:		October 2022
 54KernelVersion:	6.1
 55Contact:	Yicong Yang <yangyicong@hisilicon.com>
 56Description:	(RW) Control the allocated buffer watermark of outbound packets.
 57		The packets will be stored in the buffer first and then transmitted
 58		either when the watermark reached or when timed out.
 59		The available tune data is [0, 1, 2]. Writing a negative value
 60		will return an error, and out of range values will be converted
 61		to 2. The value indicates a probable level of the event.
 62
 63What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters
 64Date:		May 2023
 65KernelVersion:	6.5
 66Contact:	Yicong Yang <yangyicong@hisilicon.com>
 67Description:	This directory contains the files providing the PCIe Root Port filters
 68		information used for PTT trace. Each file is named after the supported
 69		Root Port device name <domain>:<bus>:<device>.<function>.
 70
 71		See the description of the "filter" in Documentation/trace/hisi-ptt.rst
 72		for more information.
 73
 74What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters/multiselect
 75Date:		May 2023
 76KernelVersion:	6.5
 77Contact:	Yicong Yang <yangyicong@hisilicon.com>
 78Description:	(Read) Indicates if this kind of filter can be selected at the same
 79		time as others filters, or must be used on it's own. 1 indicates
 80		the former case and 0 indicates the latter.
 81
 82What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/root_port_filters/<bdf>
 83Date:		May 2023
 84KernelVersion:	6.5
 85Contact:	Yicong Yang <yangyicong@hisilicon.com>
 86Description:	(Read) Indicates the filter value of this Root Port filter, which
 87		can be used to control the TLP headers to trace by the PTT trace.
 88
 89What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters
 90Date:		May 2023
 91KernelVersion:	6.5
 92Contact:	Yicong Yang <yangyicong@hisilicon.com>
 93Description:	This directory contains the files providing the PCIe Requester filters
 94		information used for PTT trace. Each file is named after the supported
 95		Endpoint device name <domain>:<bus>:<device>.<function>.
 96
 97		See the description of the "filter" in Documentation/trace/hisi-ptt.rst
 98		for more information.
 99
100What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters/multiselect
101Date:		May 2023
102KernelVersion:	6.5
103Contact:	Yicong Yang <yangyicong@hisilicon.com>
104Description:	(Read) Indicates if this kind of filter can be selected at the same
105		time as others filters, or must be used on it's own. 1 indicates
106		the former case and 0 indicates the latter.
107
108What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/requester_filters/<bdf>
109Date:		May 2023
110KernelVersion:	6.5
111Contact:	Yicong Yang <yangyicong@hisilicon.com>
112Description:	(Read) Indicates the filter value of this Requester filter, which
113		can be used to control the TLP headers to trace by the PTT trace.