debugfs-dwc-pcie

  1What:		/sys/kernel/debug/dwc_pcie_<dev>/rasdes_debug/lane_detect
  2Date:		February 2025
  3Contact:	Shradha Todi <shradha.t@samsung.com>
  4Description:	(RW) Write the lane number to be checked for detection.	Read
  5		will return whether PHY indicates receiver detection on the
  6		selected lane. The default selected lane is Lane0.
  7
  8What:		/sys/kernel/debug/dwc_pcie_<dev>/rasdes_debug/rx_valid
  9Date:		February 2025
 10Contact:	Shradha Todi <shradha.t@samsung.com>
 11Description:	(RW) Write the lane number to be checked as valid or invalid.
 12		Read will return the status of PIPE RXVALID signal of the
 13		selected lane. The default selected lane is Lane0.
 14
 15What:		/sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
 16Date:		February 2025
 17Contact:	Shradha Todi <shradha.t@samsung.com>
 18Description:	The "rasdes_err_inj" is a directory which can be used to inject
 19		errors into the system. The possible errors that can be injected
 20		are:
 21
 22		  1) tx_lcrc            - TLP LCRC error injection TX Path
 23		  2) b16_crc_dllp       - 16b CRC error injection of ACK/NAK DLLP
 24		  3) b16_crc_upd_fc     - 16b CRC error injection of Update-FC DLLP
 25		  4) tx_ecrc            - TLP ECRC error injection TX Path
 26		  5) fcrc_tlp           - TLP's FCRC error injection TX Path
 27		  6) parity_tsos        - Parity error of TSOS
 28		  7) parity_skpos       - Parity error on SKPOS
 29		  8) rx_lcrc            - LCRC error injection RX Path
 30		  9) rx_ecrc            - ECRC error injection RX Path
 31		  10) tlp_err_seq       - TLPs SEQ# error
 32		  11) ack_nak_dllp_seq  - DLLPS ACK/NAK SEQ# error
 33		  12) ack_nak_dllp      - ACK/NAK DLLPs transmission block
 34		  13) upd_fc_dllp       - UpdateFC DLLPs transmission block
 35		  14) nak_dllp          - Always transmission for NAK DLLP
 36		  15) inv_sync_hdr_sym  - Invert SYNC header
 37		  16) com_pad_ts1       - COM/PAD TS1 order set
 38		  17) com_pad_ts2       - COM/PAD TS2 order set
 39		  18) com_fts           - COM/FTS FTS order set
 40		  19) com_idl           - COM/IDL E-idle order set
 41		  20) end_edb           - END/EDB symbol
 42		  21) stp_sdp           - STP/SDP symbol
 43		  22) com_skp           - COM/SKP SKP order set
 44		  23) posted_tlp_hdr    - Posted TLP Header credit value control
 45		  24) non_post_tlp_hdr  - Non-Posted TLP Header credit value control
 46		  25) cmpl_tlp_hdr      - Completion TLP Header credit value control
 47		  26) posted_tlp_data   - Posted TLP Data credit value control
 48		  27) non_post_tlp_data - Non-Posted TLP Data credit value control
 49		  28) cmpl_tlp_data     - Completion TLP Data credit value control
 50		  29) duplicate_tlp     - Generates duplicate TLPs
 51		  30) nullified_tlp     - Generates Nullified TLPs
 52
 53		(WO) Write to the attribute will prepare controller to inject
 54		the respective error in the next transmission of data.
 55
 56		Parameter required to write will change in the following ways:
 57
 58		- Errors 9 and 10 are sequence errors. The write command:
 59
 60		    echo <count> <diff> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
 61
 62		    <count>
 63			    Number of errors to be injected
 64		    <diff>
 65			    The difference to add or subtract from natural
 66			    sequence number to generate sequence error.
 67			    Allowed range from -4095 to 4095
 68
 69		- Errors 23 to 28 are credit value error insertions. The write
 70		  command:
 71
 72		    echo <count> <diff> <vc> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
 73
 74		    <count>
 75			    Number of errors to be injected
 76		    <diff>
 77			    The difference to add or subtract from UpdateFC
 78			    credit value. Allowed range from -4095 to 4095
 79		    <vc>
 80			    Target VC number
 81
 82		- All other errors. The write command:
 83
 84		    echo <count> > /sys/kernel/debug/dwc_pcie_<dev>/rasdes_err_inj/<error>
 85
 86		    <count>
 87			    Number of errors to be injected
 88
 89What:		/sys/kernel/debug/dwc_pcie_<dev>/rasdes_event_counters/<event>/counter_enable
 90Date:		February 2025
 91Contact:	Shradha Todi <shradha.t@samsung.com>
 92Description:	The "rasdes_event_counters" is the directory which can be used
 93		to collect statistical data about the number of times a certain
 94		event has occurred in the controller. The list of possible
 95		events are:
 96
 97		1) EBUF Overflow
 98		2) EBUF Underrun
 99		3) Decode Error
100		4) Running Disparity Error
101		5) SKP OS Parity Error
102		6) SYNC Header Error
103		7) Rx Valid De-assertion
104		8) CTL SKP OS Parity Error
105		9) 1st Retimer Parity Error
106		10) 2nd Retimer Parity Error
107		11) Margin CRC and Parity Error
108		12) Detect EI Infer
109		13) Receiver Error
110		14) RX Recovery Req
111		15) N_FTS Timeout
112		16) Framing Error
113		17) Deskew Error
114		18) Framing Error In L0
115		19) Deskew Uncompleted Error
116		20) Bad TLP
117		21) LCRC Error
118		22) Bad DLLP
119		23) Replay Number Rollover
120		24) Replay Timeout
121		25) Rx Nak DLLP
122		26) Tx Nak DLLP
123		27) Retry TLP
124		28) FC Timeout
125		29) Poisoned TLP
126		30) ECRC Error
127		31) Unsupported Request
128		32) Completer Abort
129		33) Completion Timeout
130		34) EBUF SKP Add
131		35) EBUF SKP Del
132
133		(RW) Write 1 to enable the event counter and write 0 to disable
134		the event counter. Read will return whether the counter is
135		currently enabled or disabled. Counter is disabled by default.
136
137What:		/sys/kernel/debug/dwc_pcie_<dev>/rasdes_event_counters/<event>/counter_value
138Date:		February 2025
139Contact:	Shradha Todi <shradha.t@samsung.com>
140Description:	(RO) Read will return the current value of the event counter.
141		To reset the counter, counter should be disabled first and then
142		enabled back using the "counter_enable" attribute.
143
144What:		/sys/kernel/debug/dwc_pcie_<dev>/rasdes_event_counters/<event>/lane_select
145Date:		February 2025
146Contact:	Shradha Todi <shradha.t@samsung.com>
147Description:	(RW) Some lanes in the event list are lane specific events.
148		These include events from 1 to 11, as well as, 34 and 35. Write
149		the lane number for which you wish the counter to be enabled,
150		disabled, or value dumped. Read will return the current
151		selected lane number. Lane0 is selected by default.
152
153What:		/sys/kernel/debug/dwc_pcie_<dev>/ltssm_status
154Date:		February 2025
155Contact:	Hans Zhang <18255117159@163.com>
156Description:	(RO) Read will return the current PCIe LTSSM state in both
157		string and raw value.